Master of Science / Department of Electrical and Computer Engineering / Andrew Rys / Clock and data recovery (CDR) circuits form the backbone of high speed receivers. These receivers are used in various applications such as chip to chip interconnects, optical communications and backplane routing. The received data in CDR circuits are potentially noisy and asynchronous, i.e. they are not accompanied by a clock. The CDR circuit has to generate a clock from the data and then retime the data. The CDR circuit that recovers the clock and retimes the data has to remove the jitter that is accumulated during its transport through channels due to inter symbol interference (ISI). There are stringent jitter specifications defined by various communication standards that must be addressed by CDR circuits. These make the design of CDR circuits more difficult for system designers as well the circuit designer. Many parameters have to be taken into consideration while designing a CDR circuit. The problem becomes even more interesting as there are various tradeoffs in the design. As speeds of communications increase, the maximum allowable jitter decreases. Jitter in CDR circuits arises due to a lot of factors and is also dependent on the method used for clock and data recovery. In CDR circuits that use phase locked loops to recover the clock and retime the data, jitter may be caused by the metastability of sequential elements used in phase detectors. Jitter is also caused by the phase noise of the VCO used in the PLL. In CDR circuits that use the delay locked loop to recover the clock and data, jitter may be caused by the metastability of sequential elements in phase detectors as well as the quality of reference clock that is used to re-time the data. Additional effects that can cause jitter in CDR circuits include the use of spread spectrum clocking, delta sigma noise shaping performance, etc. In this thesis a non-sequential linear phase detector has been proposed which does not use any sequential elements to avoid metastability issues in phase detectors. The output jitter in a CDR circuit that uses the proposed phase detector is measured and compared to a Hogge Phase Detector [5].

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time. / Dissertation/Thesis / M.S. Electrical Engineering 2012

This work is dealing with phase lock loop design. In the theoretical part is principal description. In the practical part is detailed mathematical description, choice of various blocks, design calculation and optimalization of final solution. Designed solution is simulated and final result are commented.

This dissertation details the work has been done on a novel resonant cavity linear interferometric modulator and a direct phase detector with channel filtering capability using injection-locked semiconductor lasers for applications in RF photonics. First, examples of optical systems whose performance can be greatly enhanced by using a linear intensity modulator are presented and existing linearized modulator designs are reviewed. The novel linear interferometric optical intensity modulator based on an injection-locked laser as an arcsine phase modulator is introduced and followed by numerical simulations of the phase and amplitude response of an injection-locked semiconductor laser. The numerical model is then extended to study the effects of the injection ratio, nonlinear cavity response, depth of phase and amplitude modulation on the spur-free dynamic range of a semiconductor resonant cavity linear modulator. Experimental results of the performance of the linear modulator implemented with a multi-mode Fabry-Perot semiconductor laser as the resonant cavity are shown and compared with the theoretical model. The modulator performance using a vertical cavity surface emitting laser as the resonant cavity is investigated as well. Very low Vπ in the order of 1 mV, multi-gigahertz bandwidth (-10 dB bandwidth of 5 GHz) and a spur-free dynamic range of 120 dB.Hz2/3 were measured directly after the modulator. The performance of the modulator in an analog link is experimentally investigated and the results show no degradation of the modulator linearity after a 1 km of SMF. The focus of the work then shifts to applications of an injection-locked semiconductor laser as a direct phase detector and channel filter. This phase detection technique does not iv require a local oscillator. Experimental results showing the detection and channel filtering capability of an injection-locked semiconductor diode laser in a three channel system are shown. The detected electrical signal has a signal-to-noise ratio better than 60 dB/Hz. In chapter 4, the phase noise added by an injection-locked vertical cavity surface emitting laser is studied using a self-heterodyne technique. The results show the dependency of the added phase noise on the injection ratio and detuning frequency. The final chapter outlines the future works on the linear interferometric intensity modulator including integration of the modulator on a semiconductor chip and the design of the modulator for input pulsed light.

As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited channels. As a clock reconstructing module in a receiver, the recovered clock quality of Clock and Data Recovery is the main issue of the receiver performance. However, from unknown incoming jitter, it is difficult to optimize loop dynamics to minimize steady-state and dynamic jitter. In this thesis a 10 Gb/s adaptive loop bandwidth clock and data recovery circuit with on-chip loop filter is presented. The proposed system optimizes the loop bandwidth adaptively to minimize jitter so that it leads to an improved jitter tolerance performance. This architecture tunes the loop bandwidth by a factor of eight based on the phase information of incoming data. The resulting architecture performs as good as a maximum fixed loop bandwidth CDR while tracking high speed input jitter and as good as a minimum fixed bandwidth CDR while suppressing wide bandwidth steady-state jitter. By employing a mixed mode predictor, high updating rate loop bandwidth adaptation is achieved with low power consumption. Another relevant feature is that it integrates a typically large off-chip filter using a capacitance multiplication technique that employs dual charge pumps. The functionality of the proposed architecture has been verified through schematic and behavioral model simulations. In the simulation, the performance of jitter tolerance is confirmed that the proposed solution provides improved results and robustness to the variation of jitter profile. Its applicability to industrial standards is also verified by the jitter tolerance passing SONET OC-192 successfully.

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 μm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 μm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 μm CMOS technology.

This project deals with possibilities of using the software defined radio conception for radio amateur use in a short wave band and its subsequent implementation into properly designed hardware. The aim of this work is to design a transceiver that would be capable of working in AM, FM, SSB, and CW modes. Within a theoretical part of the project the architectures of software defined radios and their components are discussed. This part was focused mainly on analog parts of the chain, such as amplifiers, filters and converters. Signal processing algorithms for both receiver and transmitter working in desired modes are studied subsequently and their computer models are built. Designed algorithms are implemented into FPGA structure (Virtex -5).

This thesis deals with design of synchronized sources of time signal. The first part of the thesis deals with the theory the crystal resonators, crystal oscillators and PLL. The second part of the thesis deals with the crystal oscillator with 10MHz frequency. In the oscillator is use of SC cut crystal. The third part of the work deals with method of synchronization. To synchronization is use of PLL.

No description available.

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384