A voltage controlled oscillator (VCO), that generates a periodic signal whose frequency is tuned by a voltage, is a key building block in any integrated circuit systems. A sine wave oscillator can be used for a built-in self testing where high linearity is required. A bandpass filter (BPF) based oscillator is a preferred solution, and high quality factor (Q-factor) is needed to improve the linearity. However, a stringent linearity specification may require very high Q-factor, not practical to implement. To address this problem, a frequency harmonic shaping technique is proposed. It utilizes a finite impulse response filter improving the linearity by rejecting certain harmonics. A prototype SC BPF oscillator with an oscillating frequency of 10 MHz is designed and measurement results show that linearity is improved by 20 dB over a conventional oscillator. In radio frequency area, preferred oscillator structures are an LC oscillator and a ring oscillator. An LC oscillator exhibits good phase noise but an expensive cost of an inductor is disadvantageous. A ring oscillator can be built in standard CMOS process, but suffers due to a poor phase noise and is sensitive to supply noise. A RC BPF oscillator is proposed to compromise the above difficulties. A RC BPF oscillator at 2.5 GHz is designed and measured performance is better than ring oscillators when compared using a figure of merit. In particular, the frequency tuning range of the proposed oscillator is superior to the ring oscillator. VCO is normally incorporated with a frequency synthesizer (FS) for an accurate frequency control. In an integer-N FS, reference spur is one of the design concerns in communication systems since it degrades a signal to noise ratio. Reference spurs can be rejected more by either the lower loop bandwidth or the higher loop filter. But the former increases a settling time and the latter decreases phase margin. An adaptive lowpass filtering technique is proposed. The loop filter order is adaptively increased after the loop is locked. A 5.8 GHz integer-N FS is designed and measurement results show that reference spur rejection is improved by 20 dB over a conventional FS without degrading the settling time. A new pulse interleaving technique is proposed and several design modifications are suggested as a future work.

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The first topic of this thesis is a practical load-optimized VCO design for low-jitter 5V 500 MHz digital phase-locked loop. Besides the low jitter advantage, the design also possesses another feature, i.e., fast locked time. The second topic is the half-swing PLA circuit. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes of PLAs to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced. The third topic is a novel design of a the 1.0 GHz pipelining 8-bit CLA based on the architecture we mentioned in the second topic. The operating clock frequency is 1.0 GHz and the output of the addition of two 8-bit binary numbers is done in 2 cycles ( 2.0 ns ).

As an increasing number of distributed power generation systems (DPGS) are being connected to the utility grid, there is a growing requirement for the DPGS to be able to ride through short grid disturbances. This requires improvements to be made to the grid-side control scheme of the DPGS. An important part of the grid-side control scheme is the grid synchronization method, which is responsible for tracking the phase angle of the grid voltage vector. The state-of-the-art grid synchronization methods being used today are phase-locked loops. This thesis presents a modified phase-locked loop which is more robust towards grid disturbances. It consists of a multi-block adaptive notch filter (ANF) integrated into a conventional three-phase synchronous reference frame phase-locked loop (SRF-PLL). The addition of the multi-block ANF to the system allows it to become frequency adaptive. Also, since the multi-block ANF consists of multiple ANF blocks in parallel with one another, the system is able to remove multiple input signal distortions. Thus, the proposed system is able to eliminate the double frequency ripple that is caused in the conventional three-phase SRF-PLL by input unbalance, as well as harmonic errors, despite the presence of frequency variations in the input signal. Simulation results found using Matlab/Simulink, and experimental results found using the dSPACE DS1103 DSP board, demonstrate the feasibility of the modified SRF-PLL. Also, the modified SRF-PLL is compared to a conventional three-phase SRF-PLL, as well as to a conventional three-phase SRF-PLL with a simple notch filter, and the advantages of the modified SRF-PLL are discussed. / Thesis (Master, Electrical & Computer Engineering) -- Queen's University, 2008-12-17 12:38:02.589

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / FLL’s are extensively used for fast carrier synchronization. A common approach to meet the wide acquisition range and sufficiently small tracking error requirements is to adopt the wide or narrow band FLL loop in the acquisition and tracking modes and direct switching the loop. The paper analyze the influence of direct switching on performance, including the narrow band loop convergence, transition time etc. and propose applying the Kalman filtering theory to realize the seamless switching (SS) with time-varying loop gains between the two different loop tracking state. The SS control gains for the high dynamic digital spread spectrum receiver is derived. Simulation results for the SS compared to the direct switching demonstrate the improved performance.

International Telemetering Conference Proceedings / October 26-29, 1998 / Town & Country Resort Hotel and Convention Center, San Diego, California / Presentation for ITC 98 of Alcatel Espace last studies and developments regarding TTC Products This document lays on 3 parts: · a technical point of view · a technology/design description · a synthesis showing main performance and results

Made available in DSpace on 2014-06-12T17:37:50Z (GMT). No. of bitstreams: 2 arquivo5359_1.pdf: 2762932 bytes, checksum: 0ca3cda75d19c5289f1914aaa550bbc1 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2008 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / O uso de conversores de freqüência CC/CA para integrar a energia renovável como uma fonte de geração distribuída tem se tornado cada vez mais comum. Em tais aplicações, a sincronização com o vetor tensão da rede é fundamental para o controle do conversor, particularmente considerando os novos requisitos de suportabilidade a afundamentos de tensão demandados das gerações distribuídas atualmente. Este trabalho propõe um novo método de sincronização aplicado ao controle de conversores de freqüência apresentado-se imune a condições anormais de operação da rede. Quatro outros métodos de sincronização encontrados na literatura são apresentados enfatizando-se suas capacidades de fornecerem respostas corretas diante de tensões desequilibradas e distorcidas. O método proposto é simulado computacionalmente e comparado às demais técnicas. Os resultados experimentais também são mostrados, com o qual o novo método consegue eliminar a influência de desequilíbrios e harmônicos na estimação da fase, da freqüência e da magnitude do vetor tensão da rede. O método proposto é modelado como aplicado ao controle do conversor de uma turbina eólica conectada ao sistema elétrico. São implementadas duas estratégias de controle do conversor do lado da rede para avaliar a independência dos resultados em relação a técnica de controle de corrente. Afundamentos momentâneos de tensão no ponto de conexão são simulados e os resultados obtidos com o método proposto mostraram que a turbina eólica não perdeu a estabilidade

The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts.

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero determining capacitance (CZ). A low loop bandwidth CPPLL has a higher CZ value, and hence consumes a larger die area than a large loop bandwidth CPPLL. Literature survey shows that the problem of higher CZ value in low loop bandwidth CPPLL is addressed by using some form of emulation techniques. A relatively simpler emulation technique is the use of dual charge pump based loop filter. Existing dual charge pump based loop filter consume extra elements (such as summer that need opamps to realize the summer function) for achieving low CZ value. These extra elements consume extra area and additional power. We present two types of Summer-Less Dual Charge Pump (SDCP) based loop filter designs that do not need extra elements and still achieves low CZ value and this is achieved by using a second charge pump in an appropriate way. A test chip was implemented in 0.13µm UMC MMRFCMOS process to verify the presented circuits. The presented SDCP based loop filter circuits are particularly useful in designs employing multiple CPPLL’s and design employing low loop bandwidth CPPLL’s. Another challenge worth-mentioning is the frequency ranges over which the PLL can be locked. The Voltage Controlled Oscillator (VCO) of PLL mainly determines the frequency locking range of a PLL. A typical VCO has a frequency locking range of usually 1:2 to 1:3. The VCO frequency tuning range reduces with reduction in supply voltage. This poses a serious problem in low supply voltage applications that demand a wide frequency locking range, sometimes greater than 1:3. We have addressed this problem of wide PLL lock range, by using an Analog Frequency Detector. A wide frequency lock range is achieved, either by dynamically modifying the VCO or the feedback divider of PLL. Both the approaches are equally feasible. The frequency detector is used for dynamically modifying the VCO or the feedback divider of PLL. Two test chips were implemented to verify the presented Analog Frequency Detector scheme. A testchip implemented in 0.25µm CSM analog process achieves wide frequency lock range by dynamically modifying the feedback divider of PLL. Another testchip implemented in 0.13µm UMC MMRFCMOS process achieves wide frequency lock range by dynamically modifying the center frequency of the VCO. Presented analog frequency detection scheme is particularly useful in applications that demand wide PLL lock range from a single die.

The thesis uses an up-down conversion architecture to realize a wideband frequency synthesizer for digital video broadcasting (DVB) transmission system. At first, the theoretical analysis of this architecture is performed to understand the mechanism to suppress the phase noise in an optimal way. Then, the simulations using Matlab and ADS are carried out to predict the phase noise performance. Based on the above efforts, a 50 MHz ~ 1 GHz wideband frequency synthesizer hybrid circuit is implemented and its phase noise performance, corresponding to different choices of the reference sources, is finally discussed. The second part of this thesis is to extend the up-down conversion architecture to an offset phase-locked loop (PLL) architecture for wideband frequency synthesizers. The difference from the conventional offset PLLs is the phase locking of the signal at either the sum or the difference frequency of two voltage-controlled oscillators (VCOs) to the reference source for the purpose of wideband operation. The phase noise analysis of the proposed offset PLL architecture is provided. In the experiments, a 300 MHz ~ 3.6 GHz wideband frequency synthesizer hybrid circuit is implemented to verify the analyzed phase noise results. In addition, a CMOS wideband frequency synthesizer chip using the proposed offset PLL architecture has been realized. Moreover, another two CMOS wideband frequency synthesizer chips are included in this thesis. It is worth mentioning that the VCOs in these two frequency synthesizer chips use the switched capacitor and inductor techniques to achieve a wideband operation.