Biopotential signals are important to physicians for diagnosing medical conditions in patients. Traditionally, biopotentials are acquired using contact electrodes together with instrumentation amplifiers (INAs). The biopotentials are generally weak and in the presence of stronger common mode signals. The INA thus needs to have very good Common Mode Rejection Ratio (CMRR) to amplify the weak biopotential while rejecting the stronger common mode interferers. Opamp based INAs with a resistor-capacitor feedback are suitable for acquiring biopotentials with low power and low noise performance. However, CMRR of such INA topologies is typically very poor. In the presented research, a technique is proposed for improving the CMRR of opamp based INAs in RC feedback configurations by dynamically matching input and feedback capacitor pairs. Two instrumentation amplifiers (one fully differential and the other fully balanced fully symmetric) are designed with the proposed dynamic element matching scheme. Post layout simulation results show that with 1 percent mismatch between the limiting capacitor pairs, CMRR is improved to above 150dB when the proposed dynamic element matching scheme is used. The INAs draw about 10uA of quiescent current from a 1.5 dual power supply source. The input referred noise of the INAs is less than 3uV/sqrt(Hz).

The thesis deals about method of gain signals from strain gauge bridges. There are mentioned some signal conditioning methods for bridges amplifiers and charactered their properties. In the next part of this thesis are calculated the amplifier errors for various temperature. There are projected individual variants of strain gage amplifiers (instrumentation amplifier AD524, isolation amplifier, switched capacitor based instrumentation amplifier), their properties are compared with strain gage amplifier Vishay P-3500.

The growth in the number of wireless devices and applications underscores the need for characterizing and mitigating interference induced problems such as distortion and blocking. A typical interference scenario involves the detection of a small amplitude signal of interest (SOI) in the presence of a large amplitude interfering signal; it is desirable to attenuate the interfering signal while preserving the integrity of SOI and an appropriate dynamic range. If the frequency of the interfering signal varies or is unknown, an adaptive notch function must be applied in order to maintain adequate attenuation. This work explores the performance space of a phase cancellation technique used in implementing the desired notch function for communication systems in the 1-3 GHz frequency range. A system level model constructed with MATLAB and related simulation results assist in building the theoretical foundation for setting performance bounds on the implemented solution and deriving hardware specifications for the RF notch subsystem devices. Simulations and measurements are presented for a Low Noise Amplifer (LNA), voltage variable attenuators, bandpass filters and phase shifters. Ultimately, full system tests provide a measure of merit for this work as well as invaluable lessons learned. The emphasis of this project is the on-wafer LNA measurements, dependence of IC system performance on mismatches and overall system performance tests. Where possible, predictions are plotted alongside measured data. The reasonable match between the two validates system and component models and more than compensates for the painstaking modeling efforts. Most importantly, using the signal to interferer ratio (SIR) as a figure of merit, experimental results demonstrate up to 58 dB of SIR improvement. This number represents a remarkable advancement in interference rejection at RF or microwave frequencies.

This thesis presents the analysis, design and characterization of an integrated high-frequency phase-locked loop (PLL) frequency multiplier. The frequency multiplier is novel in its use of a low multiplication factor of 4 and a fully differential topology for rejection of common mode interference signals. The PLL is composed of a voltage controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has been fabricated using a standard CMOS 0.18-um process based on its relatively low cost and ready availability. The PLL frequency multiplier generates an output signal at 26 GHz and is the highest operational frequency PLL in the technology node reported to date. Time domain phase plane analysis is used for prediction of PLL locking range based on initial conditions of phase and frequency offsets. Tracking range of the PLL is limited by the inherent narrow locking range of the ILFD, and is confirmed via experimental results. The performance benefits of the fully differential PLL are experimentally confirmed by the injection of differential- and common-mode interfering signals at the VCO control lines. A comparison of the common- and differential-mode modulation indices reveals that a common mode rejection ratio (CMRR) of greater than 20 dB is possible for carrier offset frequencies of less than 1 MHz. Closed-loop frequency domain transfer functions are used for prediction of the PLL phase noise response, with the PLL being dominated by the reference and VCO phase noise contributions. Regions of dominant phase noise contributions are presented and correlated to the overall PLL phase noise performance. Experimental verifications display good agreement and confirm the usefulness of the techniques for PLL performance prediction. The PLL clock multiplier has an operational output frequency of 26.204 to 26.796 GHz and a maximum output frequency step of 16 MHz. Measured phase noise at 1 MHz offset from the carrier is -103.9 dBc/Hz. The PLL clock multiplier core circuit (VCO/ILFD/MSFF Divider/PD) consumes 186 mW of combined power from 2.8 and 4.3 V DC rails. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-24 11:31:35.384

This dissertation is aimed at the development of a current mode instrumentation amplifier (CMIA) with a high common mode input range. This characteristic is obtained due to the rail-to-rail operational amplifiers (opamps). These opamps are built with rail-to-rail differential amplifiers as input stages, and with cascode-based output stages, which are able to copy its current by adding identical branches and connecting their gates without the voltage degradation as the known CMIA topologies. The main contribution of this work is the development of a rail-to-rail current mode instrumentation amplifier, analyzing the pros and cons of this topology. The functionality of the proposed topology is shown through measured results of a manufactured integrated circuit. This first prototype, although it was operated in a large input common mode range, presented insufficient values of CMRR (Common Mode Rejection Ratio) and VOS (Offset voltage). These two characteristics were studied and modeled, the instrumentation amplifier was re-designed, and simulated results demonstrate important improvements. / Esta dissertação tem como objetivo o desenvolvimento de um amplificador de instrumentação em modo corrente com uma ampla faixa de entrada em modo comum. Esta característica é obtida graças ao emprego de estágios de amplificação rail-to-rail na entrada e a geração do sinal de saída através do espelhamento da corrente diretamente dos gates dos transistores do estágio ao invés da alternativa clássica, onde espelhos são ligados em série e degradam a excursão do sinal de saída. Com esta proposta, é possível a implementação de ampops com entrada e saída rail-to-rail. A principal contribuição deste trabalho é analisar as vantagens e desvantagens da utilização destas soluções na implementação de um amplificador de instrumentação com entrada rail-to-rail. A funcionalidade da topologia proposta é demonstrada através dos resultados medidos de um circuito integrado fabricado. Este primeiro protótipo, apesar do bom funcionamento em toda a faixa de entrada em modo comum, apresentou valores insatisfatórios de CMRR (Common Mode Rejection Ratio) e de VOS (Tensão de offset), o que levou a um aprofundamento no estudo e modelagem destas características. A partir disto, o circuito foi re-projetado e os resultados de simulação demonstram melhorias bastante significativas em suas características.