La complexité croissante des systèmes numériques amène les architectures reconfigurable telles que les Field Programmable Gate Arrays (FPGA) à être très fortement demandés en raison de leur facilité de (re)programmabilité et de leurs faibles coûts non récurrents (NRE). La re-configurabilité est réalisée grâce à de nombreux point mémoires de configuration. Cette re-configurabilité se traduit par une extrême flexibilité des applications implémentées et dans le même temps par une perte en surface, en performances et en puissance par rapport à des circuits intégrés spécifiques (ASIC) pour la même fonctionnalité. Dans cette thèse, nous proposons la conception de FPGA avec différentes technologies 3D pour une meilleure efficacité. Nous intégrons les blocs à base de mémoire résistives pour réduire la longueur des fils de routage et pour élargir l'employabilité des FPGAs pour des applications non-volatiles de faible consommation. Parmi les nombreuses technologies existantes, nous nous concentrons sur les mémoires à base d'oxyde résistif (OxRRAM) et les mémoires à pont conducteur (CBRAM) en évaluant les propriétés uniques de ces technologies. Comme autre solution, nous avons conçu un nouveau FPGA avec une intégration monolithique 3D (3DMI) en utilisant des interconnexions haute densité. A partir de deux couches avec l'approche logique-sur-mémoire, nous examinons divers schémas de partitionnement avec l'augmentation du nombre de couches actives intégrées pour réduire la complexité de routage et augmenter la densité de la logique. Sur la base des résultats obtenus, nous démontrons que plusieurs niveaux 3DMI est une alternative solide pour l'avenir de mise à l'échelle de la technologie. / The ever increasing complexity of digital systems leads the reconfigurable architectures such as Field Programmable Gate Arrays (FPGA) to become highly demanded because of their in-field (re)programmability and low nonrecurring engineering (NRE) costs. Reconfigurability is achieved with high number of point configuration memories which results in extreme application flexibility and, at the same time, significant overheads in area, performance, and power compared to Application Specific Integrated Circuits (ASIC) for the same functionality. In this thesis, we propose to design FPGAs with several 3D technologies for efficient FPGA circuits. First, we integrate resistive memory based blocks to reduce the routing wirelength and widen FPGA employability for low-power applications with non-volatile property. Among many technologies, we focus on Oxide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) devices by assessing unique properties of these technologies in circuit design. As another solution, we design a new FPGA with 3D monolithic integration (3DMI) by utilizing high-density interconnects. Starting from two layers with logic-on-memory approach, we examine various partitioning schemes with increased number of integrated active layers to reduce the routing complexity and increase logic density. Based on the obtained results, we demonstrate that multi-tier 3DMI is a strong alternative for future scaling.

With the electronic equipments becoming more and more complicated, the requirements for the power management are more and more strict. Efficient performance, high functionality, small profile, fast transient and low cost are the most wanted features for modern power management ICs, especially for mobile power. In order to reduce profile, the number of external components should be as small as possible, which means that compensator, ramp compensation, current sensor, driver and even power devices should be all implemented on a single chip, i.e. monolithic integration. Comparing with discrete switching DC-DC converter, monolithic integration brings a number of benefits and new design challenges. Besides monolithic integration, high switching frequency is another trend for power management ICs due to its higher bandwidth and the ability to further reduce external passive component size. Comparing with low frequency counterparts, high frequency switching converter design is more difficult in terms of the stability modeling, high switching loss and difficult current sensing etc. The objective of this dissertation is to study the design issues for monolithic integration of high frequency switching DC-DC converter. For this purpose, a high frequency, wide input range monolithic buck converter ASIC with fast transient response is designed based on advanced trench BCD technology. Stability is the fundamental requirement in designing switching converter ASIC. Achieving this requires an accurate loop gain design, especially for monolithically integrated high frequency switching converter since compensator is fixed on silicon and loop delay is comparable with switching cycle. Since DC-DC switching converters are time-varying system, traditional small signal analysis in SPICE cannot be directly used to simulate the loop gain of this kind of system. A periodic small signal analysis based method is proposed to analyze and simulate DC-DC switching converter inside a SPICE like simulator without the need for averaging. This general method is suitable for any switching regulators. The results are accurate comparing with average modeling and experiment results even at high frequency part. A general procedure to design loop gain is proposed. Several novel design concepts are proposed for monolithic integration of high frequency switching DC-DC converter; a novel control scheme-Cotangent Control (Ctg control) is proposed for fast transient response; In order to realize on-chip implementation of the compensator, especially for low frequency zero, active feedback compensator is developed and a general design procedure is proposed. Adaptive compensation concept is proposed to stabilize the whole system for a wide application range. Multi-stage driver and multi-section device concepts are investigated for high efficiency and low noise power stage design. And finally, a new noise insensitive lossless RC sensor is proposed for high speed current sensing. At the end of this dissertation, the test results of the fabricated chip are presented to verify the correctness of these design concepts. / Ph. D.

Ces travaux de thèse ont pour but l’évaluation et le développement de briques technologiques en silicium poreux répondant à la problématique de l’intégration monolithique 3D rattachée au concept du “more than Moore” : d’une part l’intégration sur silicium de composants passifs RF, d’autre part, la réalisation de chemins traversants d’interconnexion à fort facteur d’aspect par voie électrochimique. Dans un premier temps, différents substrats mixtes silicium / silicium poreux sont réalisés. Des inductances en cuivre, réalisées sur un substrat mésoporeux de 200 µm de profondeur et de porosité proche de 60%, atteignent des facteurs de qualité à 20 GHz jusqu’à 55% supérieurs à ceux mesurés sur silicium massif. Une perspective d’industrialisation de ce type d’application est à l’étude dans le cadre d’une thèse CIFRE. La gravure de matrices de pores à fort facteur d’aspect, bien qu’encore difficilement localisable en termes de qualité de périphérie, fait d’autre part l’objet de développements, notamment pour la fabrication de condensateurs à haute densité capacitive et de contacts d’interconnexions en cuivre. / Those thesis works deal with the evaluation and the development of porous silicon technological step in order to answer some of the monolithic integration challenges bring by the “more than Moore” problematic in microelectronics industry: on one hand, the integration on silicon of passive RF devices, on the other hand, realization by electrochemical etching of through silicon via. In a first time, several mixed porous silicon / silicon substrat are realized. Copper inductors, realized on 200 µm thick and 60% porosity mesoporous layer, show a quality factor superior to 55% to the one obtained on massive silicon. Industrialization perspectives are on the line via a CIFRE PhD convention. In a second time, several electrochemical etching process are evaluated. Among them, high aspect ratio macropore array etching, although poorly localizable, allows many perspectives: copper via and high density capacitor.

No description available.

Le récent essor des systèmes de communication sans fil implique le développement de circuits RF performants, à fort taux d’intégration, bas coût, et adaptés à la production de masse. L’intégration monolithique de systèmes RF sur silicium permet de répondre en partie à ces critères. Cependant, le silicium est responsable de pertes dans le substrat dégradant les performances des composants passifs. Pour adresser cette limite, des caissons isolants de silicium poreux peuvent être réalisés au sein du silicium (substrat mixte). Les objectifs de cette thèse sont de montrer la faisabilité de l’intégration monolithique sur substrat mixte et d’étudier son impact sur les performances de circuits RF. Ce manuscrit décrit l’élaboration des substrats mixtes et donne une comparaison des performances de composants passifs intégrés sur silicium poreux et sur substrats standards. Enfin, l’intégration monolithique de circuits RF est menée sur substrat mixte 6’’. La caractérisation de ces démonstrateurs montre une amélioration des performances par rapport au silicium. De plus, la compatibilité du substrat mixte avec un procédé industriel de microélectronique est validée. / The rapid growth of wireless systems involves the development of highly efficient, large-scale, low-cost and radio frequency (RF) systems. Monolithic integration of RF circuits on silicon can enhance the appeal of this technology further. However, in order to fully realize the next generation of system-on-chip on silicon, the losses which results in to degradation in the performances of passive components need to be addressed. This work investigates locally insulating porous silicon regions on silicon substrates, targeting highly efficient passive components. This thesis begins with a detailed description of porous silicon/silicon hybrid substrate fabrication using a novel mask. The influence of the hybrid substrate on fabricated passive device performances was studied and the results were compared to similar devices on conventional silicon substrates. Finally, monolithic integration of passive and active devices was demonstrated on 6” hybrid substrates, with performance improvements when compared with standard silicon. This work has also shown that hybrid substrates can be fully integrated into industrial scale microelectronic processes.

The application of epitaxially grown, III-V semiconductor-based nanostructures to the development of electro-optical and all-optical switches is investigated through the fabrication and testing of integrated photonic devices designed using multimode interference (MMI) waveguides. The properties and limitations of the materials are explored with respect to the operation of those devices through electrical carrier injection and optical pumping. MMI waveguide geometry was employed as it offered advantages such as a very compact device footprint, low polarization sensitivity, large bandwidth and relaxed fabrication tolerances when compared with conventional single-mode waveguide formats. The first portion of this dissertation focuses on the characterization of the materials and material processing techniques for the monolithic integration of In0.15Ga0.85As/GaAs self-assembled quantum dots (SAQD) and InGaAsP/InGaAsP multiple quantum wells (MQW). Supplemental methods for post-growth bandgap tuning and waveguide formation were developed, including a plasma treatment process which is demonstrated to reliably inhibit thermally induced interdiffusion of Ga and In atoms in In0.15Ga0.85As/GaAs quantum dots. The process is comparable to the existing approach of capping the SAQD wafer with TiO2, while being simpler to implement along-side companion techniques such as impurity free vacancy disordering. Study of plasma-surface interactions in both wafer structures suggests that the effect may be dependent on the composition of the contact layer. The second portion of this work deals with the design, fabrication, and the testing of MMI switches which are used to investigate the limits of electrical current control when employing SAQD as the active core material. A variable power splitter based on a 3-dB MMI coupler is used to analyze the effects of sub-microsecond electrical current pulses in relation to carrier and thermal nonlinearities. Electrical current controlled switching of the variable power splitter and a tunable 2 x 2 MMI coupler is also demonstrated. The third part of this dissertation explores the response of In0.15Ga0.85As/GaAs SAQD waveguide structures to photogenerated carriers. Also presented is a simple, but effective, design modification to the 2 x 2 MMI cross-coupler switch that allows control over the carrier distribution within the MMI waveguide. This technique is combined with selective-area bandgap tuning to demonstrate a compact, working, all-optical MMI based switch.

Résumé : Le transistor monoélectronique (SET) est un dispositif nanoélectronique très attractif à cause de son ultra-basse consommation d’énergie et sa forte densité d’intégration, mais il n’a pas les capacités suffisantes pour pouvoir remplacer complètement la technologie CMOS. Cependant, la combinaison de la technologie SET avec celle du CMOS est une voie intéressante puisqu’elle permet de profiter des forces de chacune, afin d’obtenir des circuits avec des fonctionnalités additionnelles et uniques. Cette thèse porte sur l’intégration 3D monolithique de nanodispositifs dans le back-end-of-line (BEOL) d’une puce CMOS. Cette approche permet d’obtenir des circuits hybrides et de donner une valeur ajoutée aux puces CMOS actuelles sans altérer le procédé de fabrication du niveau des transistors MOS. L’étude se base sur le procédé nanodamascène classique développé à l’UdeS qui a permis la fabrication de dispositifs nanoélectroniques sur un substrat de SiO2. Ce document présente les travaux réalisés sur l’optimisation du procédé de fabrication nanodamascène, afin de le rendre compatible avec le BEOL de circuits CMOS. Des procédés de gravure plasma adaptés à la fabrication de nanostructures métalliques et diélectriques sont ainsi développés. Le nouveau procédé nanodamascène inverse a permis de fabriquer des jonctions MIM et des SET métalliques sur une couche de SiO2. Les caractérisations électriques de MIM et de SET formés avec des jonctions TiN/Al2O3 ont permis de démontrer la présence de pièges dans les jonctions et la fonctionnalité d’un SET à basse température (1,5 K). Le transfert de ce procédé sur CMOS et le procédé d’interconnexions verticales sont aussi développés par la suite. Finalement, un circuit 3D composé d’un nanofil de titane connecté verticalement à un transistor MOS est réalisé et caractérisé avec succès. Les résultats obtenus lors de cette thèse permettent de valider la possibilité de co-intégrer verticalement des dispositifs nanoélectroniques avec une technologie CMOS, en utilisant un procédé de fabrication compatible. / Abstract : The single electron transistor (SET) is a nanoelectronic device very attractive due to its ultra-low power consumption and its high integration density, but he is not capable of completely replace CMOS technology. Nevertheless, the hybridization of these two technologies is an interesting approach since it combines the advantages of both technologies, in order to obtain circuits with new and unique functionalities. This thesis deals with the 3D monolithic integration of nanodevices in the back-end-ofline (BEOL) of a CMOS chip. This approach gives the opportunity to build hybrid circuits and to add value to CMOS chips without fundamentally changing the process fabrication of MOS transistors. This study is based on the nanodamascene process developed at UdeS, which is used to fabricate nanoelectronic devices on a SiO2 layer. This document presents the work done on the nanodamascene process optimization, in order to make it compatible with the BEOL of CMOS circuits. The development of plasma etching processes has been required to fabricate metallic and dielectric nanostructures useful to the fabrication of nanodevices. MIM junctions and metallic SET have been fabricated with the new reverse nanodamascene process on a SiO2 substrate. Electrical characterizations of MIM devices and SET formed with TiN/Al2O3 junctions have shown trap sites in the dielectric and a functional SET at low temperature (1.5 K). The transfer process on CMOS substrate and the vertical interconnection process have also been developed. Finally, a 3D circuit consisting of a titanium nanowire connected to a MOS transistor is fabricated and is functional. The results obtained during this thesis prove that the co-integration of nanoelectronic devices in the BEOL of a CMOS chip is possible, using a compatible process.

No presente trabalho foi realizado um estudo da viabilidade de integrar dois dispositivos ópticos: micro-lâmpadas incandescentes e filtros interferenciais com o objetivo de construir um dispositivo único com características próprias. A fabricação destes dispositivos ópticos foi feita utilizando materiais dielétricos, obtidos por deposição química a vapor assistida por plasma (PECVD), e usando técnicas convencionais de microeletrônica desenvolvidas neste laboratório. São apresentadas simulações numéricas, processo de fabricação e caracterização de cada um dos dois dispositivos ópticos assim como a caracterização do dispositivo óptico integrado obtido. As micro-lâmpadas incandescentes foram fabricadas a partir de um filamento de cromo, isolado do meio ambiente por duas camadas dielétricas de oxinitreto de silício, sendo alimentado eletricamente com uma tensão contínua com a finalidade de aumentar a temperatura do filamento até atingir a incandescência. Com a finalidade de reduzir a dissipação térmica nessa região, o filamento foi projetado e construído para ficar suspenso através de uma corrosão anisotrópica parcial do substrato de silício. Por outro lado, os filtros interferenciais foram fabricados sobre substratos de vidro a partir de uma série de camadas depositadas por PECVD alternadas de Si3N4 e SiO2, com espessuras de 240 e 340 nm e índices de refração de 1.91 e 1.46 respectivamente, com a finalidade de produzir picos de atenuação na transmitância da luz na região do visível do espectro eletromagnético. Foram construídos filtros com 9, 11 e 13 camadas. Os resultados deste trabalho mostraram que é possível realizar a integração eficiente destes dois dispositivos ópticos para produzir uma fonte luminosa que permite a filtragem de uma determinada faixa de comprimentos de onda. Foi demonstrado também que tanto a largura da faixa, como a região de filtragem, podem ser controladas através do índice de refração, espessuras e número de camadas constituintes do filtro interferencial. Os resultados das simulações numéricas mostraram-se bastante coerentes com os resultados experimentais obtidos. / In the present work was realized a study of the viability of integrating two optical devices: incandescent micro-lamps and interferometric filters with the intention of obtaining a single device with specific characteristics. The fabrication of these optical devices was made using dielectric materials, obtained by plasma-enhanced chemical vapor deposition (PECVD), and using conventional microelectronics techniques developed at this laboratory. Numeric simulations, fabrication process and characterization of each one of the two optical devices as well as the characterization of the obtained integrated optical device are presented. The incandescent microlamps were fabricated from a chromium filament, isolated from the environment by two dielectric silicon oxynitride layers, which is powered electrically with a continuous voltage with the purpose of increasing the temperature of the filament to reach the incandescence. With the purpose of reducing the thermal dissipation in that area, the filament was designed and fabricated to be suspended through a partial anisotropic etch of the silicon substrate. On the other hand, the interferometric filters were fabricated on glass substrates starting from a series of alternate Si3N4 and SiO2 layers deposited by PECVD, with thickness of 240 and 340 nm and refraction indexes of 1.91 and 1.46 respectively, with the purpose of producing light transmittance attenuation peaks in the visible region of the electromagnetic spectrum. Filters were fabricated with 9, 11 and 13 layers. The results of this work showed that it is possible to develop the efficient integration of these two optical devices to produce a luminous source that it allows the filtering of a certain range of wavelengths. It was also demonstrated that, the bandwidth as well as the filtering area, can be controlled through the refraction index, thickness and number of constituent layers of the interferometric filter. The results of the numeric simulations showed to be quite coherent with the obtained experimental results.

No presente trabalho foi realizado um estudo da viabilidade de integrar dois dispositivos ópticos: micro-lâmpadas incandescentes e filtros interferenciais com o objetivo de construir um dispositivo único com características próprias. A fabricação destes dispositivos ópticos foi feita utilizando materiais dielétricos, obtidos por deposição química a vapor assistida por plasma (PECVD), e usando técnicas convencionais de microeletrônica desenvolvidas neste laboratório. São apresentadas simulações numéricas, processo de fabricação e caracterização de cada um dos dois dispositivos ópticos assim como a caracterização do dispositivo óptico integrado obtido. As micro-lâmpadas incandescentes foram fabricadas a partir de um filamento de cromo, isolado do meio ambiente por duas camadas dielétricas de oxinitreto de silício, sendo alimentado eletricamente com uma tensão contínua com a finalidade de aumentar a temperatura do filamento até atingir a incandescência. Com a finalidade de reduzir a dissipação térmica nessa região, o filamento foi projetado e construído para ficar suspenso através de uma corrosão anisotrópica parcial do substrato de silício. Por outro lado, os filtros interferenciais foram fabricados sobre substratos de vidro a partir de uma série de camadas depositadas por PECVD alternadas de Si3N4 e SiO2, com espessuras de 240 e 340 nm e índices de refração de 1.91 e 1.46 respectivamente, com a finalidade de produzir picos de atenuação na transmitância da luz na região do visível do espectro eletromagnético. Foram construídos filtros com 9, 11 e 13 camadas. Os resultados deste trabalho mostraram que é possível realizar a integração eficiente destes dois dispositivos ópticos para produzir uma fonte luminosa que permite a filtragem de uma determinada faixa de comprimentos de onda. Foi demonstrado também que tanto a largura da faixa, como a região de filtragem, podem ser controladas através do índice de refração, espessuras e número de camadas constituintes do filtro interferencial. Os resultados das simulações numéricas mostraram-se bastante coerentes com os resultados experimentais obtidos. / In the present work was realized a study of the viability of integrating two optical devices: incandescent micro-lamps and interferometric filters with the intention of obtaining a single device with specific characteristics. The fabrication of these optical devices was made using dielectric materials, obtained by plasma-enhanced chemical vapor deposition (PECVD), and using conventional microelectronics techniques developed at this laboratory. Numeric simulations, fabrication process and characterization of each one of the two optical devices as well as the characterization of the obtained integrated optical device are presented. The incandescent microlamps were fabricated from a chromium filament, isolated from the environment by two dielectric silicon oxynitride layers, which is powered electrically with a continuous voltage with the purpose of increasing the temperature of the filament to reach the incandescence. With the purpose of reducing the thermal dissipation in that area, the filament was designed and fabricated to be suspended through a partial anisotropic etch of the silicon substrate. On the other hand, the interferometric filters were fabricated on glass substrates starting from a series of alternate Si3N4 and SiO2 layers deposited by PECVD, with thickness of 240 and 340 nm and refraction indexes of 1.91 and 1.46 respectively, with the purpose of producing light transmittance attenuation peaks in the visible region of the electromagnetic spectrum. Filters were fabricated with 9, 11 and 13 layers. The results of this work showed that it is possible to develop the efficient integration of these two optical devices to produce a luminous source that it allows the filtering of a certain range of wavelengths. It was also demonstrated that, the bandwidth as well as the filtering area, can be controlled through the refraction index, thickness and number of constituent layers of the interferometric filter. The results of the numeric simulations showed to be quite coherent with the obtained experimental results.

La problématique entourant la mise en oeuvre, la conception et le conditionnement de micro-capteurs au sein d'une application embarquée représente un enjeu industriel majeur, consiste en un vaste ensemble de défis techniques et touche à de nombreux champs de recherche scientifiques comme d'applications commerciales. Ce mémoire de thèse compile de manière pédagogique et détaillée la conception, la réalisation et l'évaluation expérimentale d'un capteur MEMS constitué d'un simple micro-filament destiné à la mesure, mutuellement, de la température, de la pression et de l'humidité d'une ambiance gazeuse, en utilisant un même et mutuel étage de conditionnement du signal – ce qui en tant que tel constitue une méthode d'intégration particulièrement originale qui est arbitrairement référencée comme "intégration totale". Aussi, le principe physique sous jacent à ce triplet de mesurage est la diffusion par conduction de la chaleur, produite par effet Joule dans l'élément sensible, à travers l'échantillon gazeux l'environnant. Ainsi, le principe de fonctionnement consiste en ce que, la réponse transitoire d'un tel ensemble permet d'une part de mettre en évidence, simultanément et de manière diagonalisable, à une température donnée, l'influence de la pression et de l'humidité sur la conductivité thermique et la capacité calorifique du couple sonde/échantillon. D'autre part, l'élément sensible est spécifiquement prévu pour que dans les conditions initiales du régime transitoire de l'échauffement, sa résistance électrique ne soit sensible qu'à la seule température ambiante, indépendamment des deux mesurandes. / Integration of micro sensors within an embedded system is a challenging task in terms of commercial application and deals with many fields of research. This report compiles a novel methodology of multi-sensor integration, from the design to the experimental evaluation. The reported MEMS gas sensor is made from a resistive micro-wire. It is designed to the sensing of temperature, pressure and humidity of a gaseous sample, at the same time, in using only a single sensing part as well as a single conditioning principle – which is by itself a new feature arbitrarily called "total integration". The physical principle involved here is heat-diffusion, where heat is produced by Joule effect within the resistive sensing part, sinking through the gaseous sample. The key is that the transient response of such a sensor enables the reading of both the sample thermal conductivity and heat capacity, depending on both humidity and pressure at a given temperature, the later being only depending upon the initial response of the sensor transient response.