Thesis (M.S.)--Ohio University, March, 1989. / Title from PDF t.p.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 108-109). Also available via the Internet.

Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 74-77). Also available on the World Wide Web.

Presented in this work is a novel design technique for a low-phase-noise high-frequency CMOS voltage-controlled oscillator. Phase noise is generated from electrical noise near DC, the oscillation frequency, and its harmonics. In CMOS technology, low-frequency flicker noise dominates the close-in phase noise of the VCO. The proposed technique minimizes the VCO phase noise by seeking to eliminate the effect of flicker noise on the phase noise. This is accomplished by canceling out the DC component of the impulse sensitivity function (ISF) corresponding to each flicker-noise source, thus preventing the up-conversion of low-frequency noise into phase noise. The proposed circuit topology is a modified version of the complementary cross-coupled transconductance VCO, where additional feedback paths are introduced such that a designer can choose the feedback ratios, transistor sizes, and bias voltages to achieve the previously mentioned design objectives. A step-by-step design algorithm is presented along with a MATLAB script to aid in the computation of the ISFs and the phase noise of the VCO. Using this algorithm, a 5-GHz VCO was designed and fabricated in a 0.18μm CMOS process, and then tested for comparison with simulated results.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references (leaves 70-72). Also available in electronic version. Access restricted to campus users.

Thesis--M. Phil., University of Hong Kong, 1987.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 95-100). Also available via the Internet.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: Allen, Mark G.; Committee Member: Divan, Deepakraj M.; Committee Member: Taylor, David G.

Thesis (M.S.)--University of Missouri-Columbia, 2005. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file viewed on (month day, year) Includes bibliographical references.

The increasing density of electronics within portable electronic devices provides the motivation to develop more compact power electronics, such as DC-DC converters. Typically, integrated circuits and each passive component, such as inductors, are discreetly packaged and mounted on printed circuit board (PCB), to implement the converter. Hence for further size reduction there has been growing interest for integration schemes such as Power supply in package (PwrSiP). However, the ultimate goal is the monolithic integration of the power supply solution, in an integration scheme known as Power Supply on Chip (PwrSoC). The economic effectiveness of the converter will be determined by the device footprint and number of processing steps required to fabricate the inductor. Hence, the motivation behind this thesis is the need for microinductors with large inductance density (inductance per device footprint) while maintaining low losses, which can be integrated with silicon IC. Furthermore, the need for thick layers will result in issues with yield and reliability of the fabricated device. Hence there is a need to identify, characterise and integrate materials with low residual stress into the microinductor fabrication process. A typical choice of inter-coil dielectric is the photo-definable epoxy SU-8. However, SU-8 suffers from intrinsic issues with high residual stress and adhesion. One possible replacement for SU-8 as a structural and dielectric layer is Parylene-C. The first objective of this thesis proposes a test-bed inductor process, which incorporates Parylene as a structural and dielectric layer and has a short turnaround time of one week. This fabrication process involves the filling of high aspect ratio gaps between copper structures with Parylene and subsequent chemical mechanical planarisation, and a test chip has been designed to characterise these processes. Additionally, Scotch-tape testing has been used to confirm suitable Parylene adhesion to patterned and unpatterned films used in this process. Subsequently, complete microinductors, with magnetic cores, have been fabricated, characterised and benchmarked against other inductor technologies and architectures reported in the literature. Parylene is expected to produce films with low residual stress due to its room temperature deposition process. However, the test-bed inductor process requires thermal treatments up to 140°C. Hence it was necessary to characterise the stress in Parylene films as a result of processing temperature and compare this to stress levels in SU-8 5 and 3005 films. This study has determined the spatial variation of residual stress in Parylene-C and SU-8 films, by combining automated measurements of strain indicator test structures and local nanoindentation measurements of Young’s modulus. These measurements have been used to wafer map strain, Young’s modulus, and subsequently residual stress in these films, as a result of processing parameter variation. It is well known that placing ferromagnetic material in close proximity to current carrying coils can further enhance the measured inductance value. However, the conductive magnetic core is also a source of loss for the microinductor. Hence, magnetic permeability, electrical resistivity and mechanical stress in the magnetic core influence the inductance value, eddy current losses and reliability of the fabricated microinductor, respectively. The ability to characterise these properties on wafer is essential for process control and verification measurements. This thesis details a test chip capable of routine measurements on NiFe films to characterise the spatial variation of these properties. Furthermore, wafer mapping measurements are reported to identify the correlation between high frequency permeability, electrical resistivity, mechanical strain and the chemical composition of two-component Permalloy film (NixFe(100-x)) electroplated on the surface of 100mm silicon wafers. Finally, MEMS-based inductor fabrication processes typically require a number of electrodeposition steps, which require conductive seed layers for the deposition of the coils and magnetic core material. A typical choice of seed layer is copper. However, due to copper’s paramagnetic behaviour (μ = 1) and low electrical resistivity (ρ=6.69μΩ.cm) this layer contributes to eddy current losses, while acting as a thin ‘screening layer’. It is very likely that using a magnetic seed layer, within the magnetic core, will noticeably reduce eddy current related losses. However, detailed systematic experimental studies on any such improvement have not been documented in the literature. This study involves compositional, structural, electrical and magnetic characterisation of Ni80Fe20 films electro-deposited on non-magnetic and magnetic seed layers (i.e. copper and nickel respectively). Mechanical strain test structures and X-ray analysis have been used to characterise the stress levels and structural properties of Ni80Fe20 films electro-deposited on both copper and nickel seed layers. In addition, planar spiral micro-inductors, both with and without patterned magnetic cores, have been fabricated to determine the effect of patterning on their performance. This is in addition to quantifying the improvement in the electrical performance resulting from the enhanced magnetic and resistive contribution provided by magnetic seed layers.