Avec le développement des technologies portables, les mémoires de type flash sont de plus en plus utilisées. Les compétences requises pour répondre au marché florissant augmentent chaque année. Cependant, les technologies actuelles sont basées sur l’intégration de transistors. Leurs performances impliquent un long temps d’écriture et des tensions d’opérations importantes. La technologie Resistive Random Access Memory (RRAM) permet de répondre aux problématiques liées aux mémoires de type flash. La simplicité de fabrication de ces mémoires permet une forte densité d’intégration à faible coût. Également, les performances attendues par cette technologie dépassent les performances actuelles de Dynamic Random Access Memory (DRAM). Les études réalisées actuellement au sein de la communauté scientifique permettent de déterminer les meilleures performances selon le choix des matériaux. Les premières études se concentraient sur l’oxyde de titane TiO2 en tant qu’isolant, puis avec l’augmentation de l’intérêt envers cette technologie le nombre d’oxydes étudiés s’est élargi. Les dispositifs conventionnels utilisent une couche d’oxyde comprise entre deux électrodes métalliques. En augmentant la densité de dispositifs dans des circuits en matrices croisées, l’isolation entre les points mémoires n’est pas garantie et les courants de fuites deviennent un facteur limitant. Pour éviter ces problèmes, le contrôle de chaque cellule est réalisé par un transistor, on parle d’architecture 1T1R avec n transistors nécessaires pour n points mémoires. En 2008 Dubuc[1] propose un nouveau procédé de fabrication: le procédé nanodamascène. En adaptant ce procédé, et en disposant deux cellules dos à dos, nous créons un composant qui ne nécessite plus de transistor de contrôle [2]. Cela permet, en outre, de réduire les courants de fuite et simplifie l’adressage de chaque cellule. Les dispositifs sont incorporés dans une couche offrant une surface planaire. Il n’y a pas de limite technique à la superposition des couches, ce qui permet une haute densité d’intégration dans le Back-end-of-line du CMOS (Complementary Metal Oxyde Semiconductor), offrant de nouveaux horizons à la technologie RRAM. Suivant les éléments précédents, mon projet de maîtrise a pour objectif de démontrer la possibilité de fabriquer des cellules RRAM en utilisant le procédé nanodamascène. Ce développement implique la fabrication, pour la première fois, de dispositifs micrométriques de type croisés et planaires en utilisant des architectures dont la fabrication est maîtrisée au sein du laboratoire. Cela permettra de mettre au point les différentes procédés de fabrication pour les deux types de dispositifs, de se familiariser avec les techniques de caractérisation électrique, d’acquérir des connaissances sur les matériaux actifs, et proposer des premiers dispositifs RRAM.

The purpose of this thesis is to research the possibility of realizing hardware support for hybrid single electron transistor (SET)-CMOS circuits by a systematic approach of design, analysis and simulation. The metallic SET transistors considered in this work are fabricated within the chip interconnect layers using CMOS back-end-of-line (BEOL)-compatible processing. The CMOS process integration can be divided into front-end-of-line (FEOL) and BEOL processes. The FEOL includes processes required to form isolated CMOS transistors whereas BEOL is the second portion of the IC fabrication where the devices get interconnected through the wiring using multiple layers of dielectrics and metals. Therefore, metallic SET circuits can be easily stacked above the CMOS platform presenting a low cost, low thermal budget, improving the overall yield at high-volume production of highly integrated systems. This considerably decreases the interconnect parasitics and increases the density of functions while maintaining the overall acceptable performance. Many problems such as low current drivability, delay and small voltage gain that hinder SET technology for its implementation in integrated circuits can be alleviated by intelligent circuit design. Although a complete replacement of CMOS by SETs is unlikely in the near future, an augmentation of CMOS with SETs is desirable if interfacing from and to CMOS works well. Interfacing from CMOS to SET circuitry is simple as the current and voltage levels are small and in accessible range. But interfacing CMOS from SET circuits is delicate due to SET logic's low current driving capability for CMOS and its interconnect. There is no concrete research on the interface issue wherein a SET-only circuitry drives a CMOS and its interconnects. For such hybridization to become possible, it is necessary to demonstrate the SET logic driving capability for CMOS with sufficient current drive and output voltage. The core SET logic can be designed to operate at low voltage, but at the interface the output of the SET logic must be in a voltage range that can be fed to a CMOS input for proper logic functionality. It is hence necessary to develop and adopt a systematic design methodology for such hybrid circuits at a specific technology node for room temperature operation. In this thesis we will look at a generalized design methodology that can be applied to (a) develop a fabrication model with parasitic effect of a hybrid SET-CMOS and SET-only circuits, (b) design and analyze the SET based fundamental building block in hybrid SET-CMOS or SET-only circuit and (c) simulate such a circuitry to assess its merits. More specifically, we will address the interfacing issue of such hybrid circuits in which we exploit the maximum capability of a SET logic in terms of driving capability, voltage response and power for a room temperature operation. The result of this research motivates the application of SET logic in 2 stages realizing some properties beyond those of CMOS devices. The first stage is the heterogeneous integration at chip level around a CMOS core. In such a circuitry, the SET introduces new functionalities such as reconfigurable logic, random number-based circuits, and multiband filtering circuits that can be combined with CMOS based general purpose processors or I/O signal restoration. The second stage of application is to use a new information processing technology focussed on a "new switch" exploiting a new state variable to provide functional scaling substantially beyond that attainable solely with ultimately scaled CMOS.

With VLSI(very large scale integration) technology shrinking and frequency increasing, the minimum feature size is smaller than sub-wavelength lithography wavelength, and the manufacturing cost is significantly increasing in order to achieve a good yield. Consequently design companies need to further lower power consumption. All these factors bring new challenges; simulation and modeling need to handle more design constraints, and need to work with modern manufacturing processes. In this dissertation, algorithms and new methodology are presented for these problems: (1) fast and accurate capacitance extraction, (2) capacitance extraction considering lithography effect, (3) BEOL(back end of line) impact on SRAM(static random access memory) performance and yield, and (4) new physical synthesis optimization flow is used to shed area and reduce the power consumption. Interconnect parasitic extraction plays an important role in simulation, verification, optimization. A fast and accurate parasitic extraction algorithm is always important for a current design automation tool. In this dissertation, we propose a new algorithm named HybCap to efficiently handle multiple planar, conformal or embedded dielectric media. From experimental results, the new method is significantly faster than the previous one, 77X speedup, and has a 99% memory savings compared with FastCap and 2X speedup, and has an 80% memory savings compared with PHiCap for complex dielectric media. In order to consider lithography effect in the existing LPE(Layout Parasitic Extraction) flow, a modified LPE flow and fast algorithms for interconnect parasitic extraction are proposed in this dissertation. Our methodology is efficient, compatible with the existing design flow and has high accuracy. With the new enhanced parasitic extraction flow, simulation of BEOL effect on SRAM performance becomes possible. A SRAM simulation model with internal cell interconnect RC parasitics is proposed in order to study the BEOL lithography impact. The impact of BEOL variations on memory designs are systematically evaluated in this dissertation. The results show the power estimation with our SRAM model is more accurate. Finally, a new optimization flow to shed area blow in the design synthesis flow is proposed, which is one level beyond simulation and modeling to directly optimize design, but is also built upon accurate simulations and modeling. Two simple, yet efficient, buffering and gate sizing techniques are presented. On 20 industrial designs in 45nm and 65nm, our new work achieves 12.5% logic area growth reduction, 5.8% total area reduction, 10% wirelength reduction and 770 ps worst slack improvement on average.

Une alternative à la réduction des dimensions caractéristiques des transistors est la 3D séquentielle. L’intégration 3D séquentielle requiert la fabrication de plusieurs niveaux de composant directement les uns au dessus des autres. Les procédés de fabrication utilisables pour les niveaux supérieurs sont limités par le budget thermique maximal que peuvent supporter les niveaux inférieurs. Pour la technologie FDSOI cette limite est fixée entre 500 °C et 550°C, 5 h dépendant de la siliciuration utilisée. Malgré le travail fourni pour réduire le BT des procédés de fabrication du transistor FDSOI, il est difficile d’atteindre cette limite pour certaines étapes, comme l’épitaxie des sources et drains surélevés. Dans ce contexte, cette thèse propose d’étudier et d’améliorer la stabilité thermique des niveaux bas, c’est à dire des transistors FDSOI et des niveaux de routages intermédiaires. L’étude de stabilité thermique du transistor FDSOI a permis d’identifier le siliciure comme étant l’élément le plus sensible aux budgets thermiques. Sa détérioration entraîne la dégradation de la résistance d’accès du transistor et favorise la diffusion du siliciure dans le canal. L’utilisation du Ni0.90Pt0.10 est limitée à 500 °C, 5 h, celle du Ni0.85Pt0.15 à 550 °C, 5 h. En alternative au NiPt, un nouveau siliciure a été étudié : le Ni0.90Co0.10. Afin de repousser sa stabilité thermique à 600 °C, 2 h, son intégration a dû être couplée à deux facteurs d’améliorations : l’amorphisation partielle des sources et drains par implantation et l’intégration d’un film de silicium intrinsèque epitaxié au-dessus des sources et drains composés de Si0.70Ge0.30. Les effets de ces différents « boosters » ont ainsi été analysés et expliqués. Pour la première fois, les avancées obtenues ont été implémentées sur des dispositifs FDSOI du noeud 14 nm. Ce premier essai est concluant car des performances identiques aux transistors pMOS fabriqués avec le siliciure Ni0.85Pt0.15, étudié depuis les années 2000, ont été obtenues. Néanmoins, la stabilité thermique évaluée sur transistor Ni0.90Co0.10 reste à améliorer. L’intégration de niveaux de routage entre les niveaux de transistors requiert des matériaux thermiquement stables et peu contaminants. Dans cette optique, la stabilité thermique d’une liste de diélectriques a été étudiée et caractérisée principalement par ellipsométrie, FTIR et ellipsométrie-porosimértie. Ainsi des couples isolant/barrière ont pu être déterminés pour chaque budget thermique appliqué entre 500 °C et 600 °C, 2 h. En ce qui concerne le métal intermédiaire, le tungstène a été étudié comme matériau conducteur, en plus du cuivre, en raison de son caractère moins contaminant. Ces deux matériaux ont montré une bonne stabilité thermique : jusqu’à 500 °C, 2 h pour le cuivre et 550 °C, 5 h pour le tungstène. Cependant, la résistance d'une ligne en cuivre est six fois moins résistante d'une ligne en tungstène. Cette valeur pourra être abaissée dans le cas de l’utilisation d’une nouvelle barrière en tungstène sans fluore qui a été étudiée et intégrée avec succès. Pour finir, la fiabilité du diélectrique à l’état de l’art, le SiOCH poreux, a été analysé dans des structures intégrant des lignes en tungstène. Dans ces conditions, la durée de vie du diélectrique est estimée à 1e16 années. Malgré la diminution de cette valeur après budget thermique à 600 °C, 2 h, (1e7 années), celle-ci reste bien supérieure à celle du cuivre dans des conditions identiques. / The 3D sequential integration is a smart alternative to planar device scaling. In this integration, the stacked transistors are processed sequentially, thus implying the reduction of the top thermal budget processes in order to preserve the bottom levels. For the FDSOI technology, the maximum thermal budget is set at 500 °C, 2 h. Despite the work done to reduce the thermal budget of the FDSOI processes, it is difficult to comply with this limit, as for example for the epitaxial raised source and drain which would need a thermal budget limit relaxation. In the frame of this Ph.D work, the thermal stability of the FDSOI transistors and the intermediate Back-End-Of-Line have been studied and optimized. The FDSOI transistor silicide has been identified as the most sensitive element to the thermal budget. Its degradation imply the access resistance degradation and favor the diffusion of the silicide into the channel. For this purpose, the Ni0.90Co0.10 silicide has been studied. To increase its thermal stability up to 600 °C, 2 h, two enhancers have been integrated: the pre-amorphization implant and the integration of a silicon capping over the Si0.70Ge0.30 source and drain. The effects of these enhancers on the thermal stability have been analyzed and understood. In addition to those, the Ni0.90Co0.10 has been integrated for the first time on 14 nm node FDSOI transistors. This first attempt is positive: identical performances on pMOS transistors have been obtained with Ni0.90Co0.10 silicide compare to Ni0.85Pt0.15 silicide, which is studied since the 2000’s. However, the improvement of thermal stability is not yet achieved on FDSOI transistors with Ni0.90Co0.10 silicide. Concerning the stability of the intermediate BEOL, the stability of dielectrics has first been studied and characterized by ellipsometry, FTIR and ellipsometric–porosimetry. Thus, insulating/barrier pairs have been defined for each thermal budget between 500 °C and 600 °C, 2 h. The metal lines have been studied using a 28nm node layout. Due to its limited contaminant characteristic, tungsten has been analyzed in addition to copper. Both materials show a good thermal stability: 500 °C, 2 h for copper and 550 °C, 5 h for tungsten despite the higher resistivity of tungsten. A factor 6 has been measured between these two materials. The resistance of a tungsten line has been improved by the integration of a new barrier. Finally, the state of the art Back-End-Of-Line dielectric reliability, the porous SiOCH, has been studied, function of the thermal budget, in structure integrated tungsten metal lines. In these conditions, the dielectric lifetime is estimated at 1e16 years. Despite its reduction due to thermal budget at 600 °C, 2 h (1e7 years), the tungsten lifetime estimation remains higher than the one obtained with copper lines without thermal budget.

Moore's law has defined the semiconductor industry for the past 50 years. Devices continue to become smaller and increasingly integrated into the world around us. Beginning with personal computers, devices have become integrated into watches, phones, cars, clothing and tablets among other things. These devices have expanded in their functionality as well as their ability to communicate with each other through the internet. Further, devices have increasingly been required to have diverse of functionality. This combination of smaller devices coupled with diversification of device functionality has become known as more than Moore. In this thesis, more than Moore applications of graphene are explored in-depth. Graphene was discovered experimentally in 2004 and since then has fueled tremendous research into its various potential applications. Graphene is a desirable candidate for many applications because of its impressive electronic and mechanical properties. It is stronger than steel, the thinnest known material, and has high electrical conductivity and mobility. In this thesis, the potentials of graphene are examined for pressure sensors, humidity sensors and transistors. Through the course of this work, high sensitivity graphene pressure sensors are developed. These sensors are orders of magnitude more sensitive than competing technologies such as silicon nanowires and carbon nanotubes. Further, these devices are small and can be scaled aggressively. Research into these pressure sensors is then expanded to an exploration of graphene's gas sensing properties -- culminating in a comprehensive investigation of graphene-based humidity sensors. These sensors have rapid response and recovery times over a wide humidity range. Further, these devices can be integrated into CMOS processes back end of the line. In addition to CMOS Integration of these devices, a wafer scale fabrication process flow is established. Both humidity sensors and graphene-based transistors are successfully fabricated on wafer scale in a CMOS compatible process. This is an important step toward both industrialization of graphene as well as heterogeneous integration of graphene devices with diverse functionality. Furthermore, fabrication of graphene transistors on wafer scale provides a framework for the development of statistical analysis software tailored to graphene devices. In summary, graphene-based pressure sensors, humidity sensors, and transistors are developed for potential more than Moore applications. Further, a wafer scale fabrication process flow is established which can incorporate graphene devices into CMOS compatible process flows back end of the line. / <p>QC 20160610</p>

With the continued progression of Moore’s law into the sub-14nm technology nodes, interconnect RC and power dissipation scaling play an increasingly important role in overall product performance. As critical dimensions in the mainstream Cu/ULK interconnect system shrink below 30nm, corresponding increases in relative process variation and decreases in overall process window mandate increasingly complex integrated solutions. Traditional metallization processes, e.g. PVD barrier and seed layers, no longer scale for all layout configurations as they reach physical and geometric limitations. Interactions between design, OPC, and patterning also play more and more critical roles with respect to reliability and yield in volume manufacturing; stated simply, scaling is no longer “business as usual”. Restricted design layouts, prescriptive design rules, novel materials, and holistic integration solutions each therefore become necessary to maximize available process windows, thus enabling new generations of cost-competitive products in the marketplace.

With the recent increase in Gold (Au) wire cost Copper (Cu) wire becomes an attractive way to manage overall package cost. On the other hand, Copper wire bonding introduces much higher mechanical impact to underlying BEoL structures and actives because of the higher stiffness and lower ductility of Copper compared to Gold. These trends are accompanied by the application of new porous or nano-particle filled materials like low-k and ultra low-k materials for Back-end of Line (BEoL) layers of advanced CMOS technologies. As a result, higher delamination and cracking risks in BEoL structures underneath bonded areas represent an increasing challenge for the thermo-mechanical reliability requirements. To overcome the related reliability issues the authors performed a two level nonlinear FEM-simulation approach. Initially nonlinear axi-symmetric modeling and simulation of the copper bonding process are coupled with a spatial simulation model of the whole BeoL and bond pad structure. Cracking and delamination risks are estimated by a surface based cohesive contact approach and the utilization of a crushing foam constitutive material model for ultra low-k materials.

Chemical systems containing oxidants are widely used at various stages in semiconductor processing, particularly for wet cleaning and polishing applications. This dissertation presents a series of studies related to oxidative removal of materials in the Front-End-Of-Line (FEOL) and Chemical Mechanical Planarization (CMP) processes during IC fabrication. In the first part of this study, stripping of photoresists exposed to high dose of ions (1E16 As/cm²) was investigated in activated hydrogen peroxide systems. Stripping of photoresists (PR) exposed to high dose (>1E15/cm²) ion beams is one of the most challenging steps in FEOL processing. This is due to unreactive crust layer that forms on the resist surface during ion implantation. The use of hydrogen peroxide systems activated by metal ion or UV light, for disrupting crust formed on deep UV resist to enable complete removal of crust as well as underlying photoresist was investigated. A systematic evaluation of variables such as hydrogen peroxide and metal ion concentration, UV intensity, temperature and time was conducted and an optimal formulation capable of attacking the crust was developed. A two step process involving pretreatment with activated hydrogen peroxide solution, followed by treatment with sulfuric acid-hydrogen peroxide mixture (SPM) was developed for complete removal of crusted resist films. In the second part of this study, electrochemically enhanced abrasive removal of Ta/TaN films was investigated in solutions containing 2,5 dihydroxy benzene sulfonic acid (DBSA) and potassium iodate (KIO₃). This method known as Electrically-assisted Chemical Mechanical Planarization (ECMP) is generating a lot of interest in IC manufacturing. Ta/TaN films were abraded at low pressures (<0.5 psi) on a polyurethane pad under galvanostatic conditions. The effect of variables including pH, KIO3 concentration, and current density has been explored. In the optimized formulation, tantalum and tantalum nitride removal rates of ~170 A⁰/min and ~200 A⁰/min, respectively have been obtained at a current density of 1 mA/cm². The use of benzotriazole as a copper inhibitor was required to obtain Ta to Cu selectivity of 0.8:1. Additionally, the nature of the oxide film formed on tantalum during the electrochemical abrasion process was characterized.

Cette thèse porte principalement sur la caractérisation électrique et la modélisation physique d'éléments mémoires émergents de type OxRRAM (Oxide Resistive Random Access Memory) intégrant soit un oxyde de nickel, soit un oxyde de hafnium. Une fois la maturité technologique atteinte, ce concept de mémoire est susceptible de remplacer la technologie Flash qui fait encore figure de référence. Les principaux avantages de la technologie OxRRAM reposent sur une très bonne compatibilité avec les filières CMOS, un faible nombre d'étapes de fabrication, une grande densité d'intégration et des performances attractives en termes de fonctionnement. Le premier objectif de ce travail concerne le diélectrique employé dans les cellules. Il s'agit d'apporter des éléments factuels permettant d'orienter un choix technologique sur la méthode d'élaboration de l'oxyde de nickel (oxydation thermique ou pulvérisation cathodique réactive) puis d'évaluer les performances de cellules à base d'oyxde de hafnium. Le second objectif est d'approfondir la compréhension des mécanismes physiques responsables du changement de résistance des dispositifs mémoire par une approche de modélisation physique des phénomènes opérant lors des phases d'écriture et d'effacement, sujet encore largement débattu dans la communauté scientifique. Le troisième objectif de cette thèse est d'évaluer, par le biais de caractérisations électriques, les phénomènes parasites intervenant dans les éléments mémoires de type 1R (élément résistif sans dispositif d'adressage) et, en particulier, la décharge capacitive apparaissant lors de leur programmation (opérations d'écriture). / This work is focused on the electrical characterization and physical modeling of emerging OxRRAM memories (Oxide Resistive Random Access Memory) integrating nickel or hafnium oxide. After reaching maturity, this memory concept is likely to replace the Flash technology which is still a standard in the CMOS industry. The main advantages of resistive memories technology is their good compatibility with CMOS processes, a small number of manufacturing steps, a high integration density and their attractive performances in terms of memory operation. The first objective of this thesis is to provide enough informations allowing to orientate the elaboration process of the active nickel oxide layer (thermal oxidation, reactive sputtering) then to compare the performances of the fabricated cells with devices featuring a hafnium oxide layer. The second objective is to understand the physical mechanisms responsible of the device resistance change. A physical model is proposed allowing to apprehend SET and RESET phenomenon in memory devices, subject which is still widely debated in the scientific community. The third objective of this thesis is to evaluate electrical parasitic phenomenon observed in 1R-type memory elements (resistive element without addressing device), in particular the parasitic capacitance appearing during cell programming (writing operation).

Intégrées aux niveaux des interconnexions en technologies CMOS et BiCMOS, les inductances doivent répondre aux critères de fortes performances électriques, faible surface et/ou forts courants. Mais le défi n'est pas simple à relever. En effet, l'évolution du Back-End Of Line (BEOL) des technologies CMOS avancées et l'utilisation d'un substrat silicium à pertes tendent à dégrader fortement leurs performances. Ainsi, le développement de BEOL optimisés pour les inductances intégrées apparaît comme indispensable si on veut pouvoir répondre aux spécifications des circuits RF visés.<br />Le principal objectif de cette thèse est de fournir des choix technologiques pour l'optimisation des inductances intégrées sur silicium, visant les applications dans la bande de fréquences de 1 à 5 GHz. <br />Tout d'abord, une stratégie de gestion des inserts métalliques à l'échelle de l'inductance a été évaluée, afin de satisfaire les règles de densité imposées dans les technologies avancées (jusqu'au nœud technologique 32 nm).<br />La volonté actuelle d'intégrer le module dédié à l'amplificateur de puissance en technologie CMOS a soulevé récemment la problématique de la gestion de forts courants (jusqu'à 1 A à 125°C) qui ne peut être adressée avec un BEOL standard. Un BEOL innovant utilisant deux niveaux de cuivre épais a été étudié en technologie CMOS 65 nm<br />Ce même BEOL a été évalué en technologie SOI. Cette dernière commence à émerger pour l'intégration du module d'émission complet en technologie CMOS de part sa compatibilité avec des substrats silicium Hautement Résistifs. L'optimisation d'inductances utilisant ce module double cuivre épais a été menée en technologie CMOS HR SOI 130 nm.