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Semiconductor manufacturing is one of the most complex existing manufacturing systems. It requires constant improvement to meet demands and expectations. This dissertation studies semiconductor manufacturing under three main topics, preventive maintenance scheduling, lot size management and AMHS scheduling. We first provide an optimization based decomposition algorithm and a heuristic algorithm to solve preventive maintenance scheduling problem along with direct optimization. Then, we develop an analytic tool to investigate and find optimal lot sizes to run in a manufacturing environment to minimize cycle time. Finally, we propose an optimization based AMHS scheduling algorithm and compare its performance to a myopic algorithm. / text

As electrical devices shrink to the atomic scale, it is expected that Moore's law will soon be obsolete for semiconductor devices. In 1974, Avriam and Ratner predicted that organic devices could replace semiconductor technology, leading to extensive research on molecular-based organic devices. This dissertation delves into the theoretical frameworks used to examine the transport in molecular junctions and aims to enhance our comprehension of charge transport and conduction properties. The studies presented in this thesis illustrates that a molecule's alteration by just a single atom can change it from an insulator to a conductor, and also that, by fine-tuning the molecule-electrode coupling strength and the tunneling distance in a molecular junction, the mechanism of charge transport across molecular wires can be switched between the normal and Inverted Marcus regions. The dissertation also presents molecular devices that function as reliable electrical switches, both static and dynamic. The findings of this research provide evidence of the feasibility of organic devices, including rectifiers and switches, with applications ranging from traditional semiconductor device replacement to neuromorphic computing.

A formidable challenge in the present multi-step Cu CMP process, employed in the ultra-large-scale integration (ULSI) technology, is the control of wafer surface non-uniformity, which primarily is due to dielectric erosion and Cu dishing. In contrast with the earlier experimental and semi-theoretical investigations, a systematic way of characterizing and modeling dielectric erosion in both single- and multi-step Cu CMP processes is presented in this paper. Wafer- and die-level erosion are defined, and the plausible causes of erosion at each level are identified in terms of several geometric and physical parameters. Experimental and analytical means of determining the model parameters are also outlined. The local pressure distribution is estimated at each polishing stage based on the evolving pattern geometry and pad deformation. The single-step model is adapted for the multi-step polishing process, with multiple sets of slurry selectivities, applied pressure, and relative velocity in each step. Finally, the effect of slurry-switching point on erosion was investigated for minimizing dielectric erosion in the multi-step Cu CMP. Based on the developed multi-step erosion model, the physical significance of each model parameter on dielectric erosion is determined, and the optimal polishing practices for minimizing erosion in both multi-step and single-step polishing are suggested. / Singapore-MIT Alliance (SMA)

The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested. / Singapore-MIT Alliance (SMA)

Slit valves play an important role in semiconductor manufacturing industry. They enable creation of a vacuum environment required for wafer processing. Due to the high volume of production in the modern semiconductor industry, slit valves experience severe degradation over their useful lifetime. If maintenance is not applied in due time, degraded valves may lead to defects in end products because of pressure loss and particle generation. In this thesis, we proposed methods for signal processing and feature extraction for analysis of slit valve vibration signatures. These methods would be used to demonstrate the ability of reliably, accurately and efficiently distinguish between each individual valve via a multi-class classification procedure. Such ability is a clear illustration of the feasibility of vibration based monitoring of the slit valve conditions. / text

In the current era of globalization in supply chain, business continuity planning should play an even more important role than previously. Business continuity planning provides company with an analysis of potential business threatening situations, everything from natural disasters to supply shortages, and ensures that actions are taken in order to mitigate the probability that those risks will become reality. Business continuity planning does not come without a cost, since companies will in some cases have to spend money in actions like redundancies (e.g. supplier). In the Semiconductor industry, supply chains might are extremely complex and globalized. These supply chains can go from having suppliers in the United States, to front-end manufacturing in Europe, to back-end manufacturing and packaging in Asia. Raw materials for semiconductor manufacturing, for example raw wafers, can be found for above $500 per wafer. It is due to not only the complexity of the supply chain in semiconductors, but also due to the high costs of raw materials and manufacturing, that it is crucial for companies in this particular industry to ensure business continuity planning is taken seriously, and adequate measures are taken to mitigate as many risks to their supply chain as possible. / text

The problems to be solved in this thesis were 1) development of a broadband RF preamplifier to be used with non-ferrous current probes so that the amplified signal exceeds the errors due to cable pickup, no detection is needed in this application, and 2) development of a self-contained device that amplifies and detects the output from a nonferrous current probe, providing a digital readout of the current. These instruments have been completed and are being tested for use by the National Institutes of Occupational Safety and Health (NIOSH). The self-contained current meter operates at frequencies up to 600 MHz, and detects currents as low as 8 mA . At these current magnitudes, the probe (pick-up coil) will output a voltage of 500μV (-53 dBm on 50Ω) which will have to be raised above 0 dBm. The final circuit uses a RF mixer as a variable attenuator in order to increase the dynamic range, two Monolithic Microwave Integrated Circuits (MMIC) for preamplification, a final broadband amplifier to raise the output compression point, a Schottky diode detector, a sample and hold circuit, and a liquid crystal digital panel meter.

Since the outset of IC Semiconductor market there has been a gap between its design and manufacturing communities. This gap continued to grow as the device geometries started to shrink and the manufacturing processes and tools got more complex. This gap lowered the manufacturing yield, leading to higher cost of ICs and delay in their time to market. It also impacted performance of the ICs, impacting the overall functionality of the systems they were integrated in. However, in the recent years there have been major efforts to bridge the gap between design and manufacturing using software solutions by providing closer collaborations techniques between design and manufacturing communities. The root cause of this gap is inherited by the difference in the knowledge and skills required by the two communities. The IC design community is more microelectronics, electrical engineering and software driven whereas the IC manufacturing community is more driven by material science, mechanical engineering, physics and robotics. The cross training between the two is almost nonexistence and not even mandated. This gap is deemed to widen, with demand for more complex designs and miniaturization of electronic appliance-products. Growing need for MEMS, 3-D NANDS and IOTs are other drivers that could widen the gap between design and manufacturing. To bridge this gap, it is critical to have close loop solutions between design and manufacturing This could be achieved by SMART automation on both sides by using Artificial Intelligence, Machine Learning and Big Data algorithms. Lack of automation and predictive capabilities have even made the situation worse on the yield and total turnaround times. With the growing fabless and foundry business model, bridging the gap has become even more critical. Smart Manufacturing philosophy must be adapted to make this bridge possible. We need to understand the Fab-fabless collaboration requirements and the mechanism to bring design to the manufacturing floor for yield improvement. Additionally, design community must be educated with manufacturing process and tool knowledge, so they can design for improved manufacturability. This study will require understanding of elements impacting manufacturing on both ends of the design and manufacturing process. Additionally, we need to understand the process rules that need to be followed closely in the design phase. Best suited SMART automation techniques to bridge the gap need to be studied and analyzed for their effectiveness.

<p>The continuous reduction of feature size in silicon-based electronic integrated circuits (ICs) is accompanied by devastating propagation delay time and power consumption that have become known as the “Interconnect Bottleneck”. Optical interconnection is a proposed solution that is poised to revolutionize the data transmission both within and between ICs. By forming the optical transmission and functional elements from silicon, they can be monolithically incorporated with standard ICs using the established CMOS (Complementary Metal Oxide Semiconductor) infrastructure with minimal incremental cost. A key required functional element is the photodetector, which provides optical-toelectrical conversion of signals. In this thesis, a method of achieving such conversion is explored, which uses the optical absorption at 1550 nm wavelengths provided by lattice defects. The physics governing defect-enhanced silicon waveguide photodiode operation is described, and a device model is used to verify the posited detection process and propose design improvements. The model was used to design a novel photodetector structure using a waveguide formed by the LOCOS (LOCal Oxidation of Silicon) process with a poly-silicon self-aligned contact. The fabricated device exhibited a responsivity of 47 mA/W, providing an improvement over previous devices of similar dimensions, although were ultimately limited by the quality of the poly-silicon/silicon interface. A sub-micron waveguide photodiode fabrication process using electron-beam lithography was developed, which produced photodiodes with responsivities of 490 mA/W. This process was used to integrate photodiodes onto micro-ring resonators, which exhibit resonant enhanced photocurrent. The physics of this enhancement were explored, and found to produce a 50 μm long resonant photodiode of responsivity equal to that of a 3 mm long non-resonant photodiode. Lastly, the integration of such sub-micron photodiodes as functioning power monitors throughout photonic circuits was demonstrated as a means to characterize and tune micro-rings during operation.</p> / Doctor of Philosophy (PhD)