Non-volatile memories (NVM) including flash memories and resistive memories have attracted significant interest as data storage media. Flash memories are widely employed in mobile devices and solid-state drives (SSD). Resistive memories are promising as storage class memory and embedded memory applications. Data reliability is the fundamental requirement of NVM as data storage media. However, modern nano-scale NVM suffers from challenges of inter-cell interference (ICI), charge leakage, and write endurance, which threaten the reliability of stored data. In order to cope with these adverse effects, advanced coding techniques including soft decision decoding have been investigated actively. However, current coding techniques do not capture the physical properties of NVM well, so the improvement of data reliability is limited. Although soft decision decoding improves the data reliability by using soft decision values, it degrades read speed performance due to multiple read operations needed to obtain soft decision values. In this dissertation, we explore coding schemes that use side information corresponding to the physical phenomena to improve the data reliability significantly. The side information is obtained before writing data into memory and incorporated during the encoding stage. Hence, the proposed coding schemes maintain the read speed whereas the write speed performance would be degraded. It is a big advantage from the perspective of speed performance since the read speed is more critical than the write speed in many memory applications. First, this dissertation investigates the coding techniques for memory with stuckat defects. The idea of coding techniques for memory with stuck-at defects is employed to handle critical problems of flash memories and resistive memories. For 2D planar flash memories, we propose a coding scheme that combats the ICI, which is a primary challenge of 2D planar flash memories. Also, we propose a coding scheme that reduces the effect of fast detrapping, a degradation factor in 3D vertical flash memories. Finally, we investigate the coding techniques that improve write endurance and power consumption of resistive memories.

abstract: This work investigates the effects of ionizing radiation and displacement damage on the retention of state, DC programming, and neuromorphic pulsed programming of Ag-Ge30Se70 conductive bridging random access memory (CBRAM) devices. The results show that CBRAM devices are susceptible to both environments. An observable degradation in electrical response due to total ionizing dose (TID) is shown during neuromorphic pulsed programming at TID below 1 Mrad using Cobalt-60. DC cycling in a 14 MeV neutron environment showed a collapse of the high resistance state (HRS) and low resistance state (LRS) programming window after a fluence of 4.9x10^{12} n/cm^2, demonstrating the CBRAM can fail in a displacement damage environment. Heavy ion exposure during retention testing and DC cycling, showed that failures to programming occurred at approximately the same threshold, indicating that the failure mechanism for the two types of tests may be the same. The dose received due to ionizing electronic interactions and non-ionizing kinetic interactions, was calculated for each ion species at the fluence of failure. TID values appear to be the most correlated, indicating that TID effects may be the dominate failure mechanism in a combined environment, though it is currently unclear as to how the displacement damage also contributes to the response. An analysis of material effects due to TID has indicated that radiation damage can limit the migration of Ag+ ions. The reduction in ion current density can explain several of the effects observed in CBRAM while in the LRS. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

abstract: Programmable metallization cell (PMC) technology is based on an electrochemical phenomenon in which a metallic electrodeposit can be grown or dissolved between two electrodes depending on the voltage applied between them. Devices based on this phenomenon exhibit a unique, self-healing property, as a broken metallic structure can be healed by applying an appropriate voltage between the two broken ends. This work explores methods of fabricating interconnects and switches based on PMC technology on flexible substrates. The objective was the evaluation of the feasibility of using this technology in flexible electronics applications in which reliability is a primary concern. The re-healable property of the interconnect is characterized for the silver doped germanium selenide (Ag-Ge-Se) solid electrolyte system. This property was evaluated by measuring the resistances of the healed interconnect structures and comparing these to the resistances of the unbroken structures. The reliability of the interconnects in both unbroken and healed states is studied by investigating the resistances of the structures to DC voltages, AC voltages and different temperatures as a function of time. This work also explores replacing silver with copper for these interconnects to enhance their reliability. A model for PMC-based switches on flexible substrates is proposed and compared to the observed device behavior with the objective of developing a formal design methodology for these devices. The switches were subjected to voltage sweeps and their resistance was investigated as a function of sweep voltage. The resistance of the switches as a function of voltage pulse magnitude when placed in series with a resistance was also investigated. A model was then developed to explain the behavior of these devices. All observations were based on statistical measurements to account for random errors. The results of this work demonstrate that solid electrolyte based interconnects display self-healing capability, which depends on the applied healing voltage and the current limit. However, they fail at lower current densities than metal interconnects due to an ion-drift induced failure mechanism. The results on the PMC based switches demonstrate that a model comprising a Schottky diode in parallel with a variable resistor predicts the behavior of the device. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

La complexité croissante des systèmes numériques amène les architectures reconfigurable telles que les Field Programmable Gate Arrays (FPGA) à être très fortement demandés en raison de leur facilité de (re)programmabilité et de leurs faibles coûts non récurrents (NRE). La re-configurabilité est réalisée grâce à de nombreux point mémoires de configuration. Cette re-configurabilité se traduit par une extrême flexibilité des applications implémentées et dans le même temps par une perte en surface, en performances et en puissance par rapport à des circuits intégrés spécifiques (ASIC) pour la même fonctionnalité. Dans cette thèse, nous proposons la conception de FPGA avec différentes technologies 3D pour une meilleure efficacité. Nous intégrons les blocs à base de mémoire résistives pour réduire la longueur des fils de routage et pour élargir l'employabilité des FPGAs pour des applications non-volatiles de faible consommation. Parmi les nombreuses technologies existantes, nous nous concentrons sur les mémoires à base d'oxyde résistif (OxRRAM) et les mémoires à pont conducteur (CBRAM) en évaluant les propriétés uniques de ces technologies. Comme autre solution, nous avons conçu un nouveau FPGA avec une intégration monolithique 3D (3DMI) en utilisant des interconnexions haute densité. A partir de deux couches avec l'approche logique-sur-mémoire, nous examinons divers schémas de partitionnement avec l'augmentation du nombre de couches actives intégrées pour réduire la complexité de routage et augmenter la densité de la logique. Sur la base des résultats obtenus, nous démontrons que plusieurs niveaux 3DMI est une alternative solide pour l'avenir de mise à l'échelle de la technologie. / The ever increasing complexity of digital systems leads the reconfigurable architectures such as Field Programmable Gate Arrays (FPGA) to become highly demanded because of their in-field (re)programmability and low nonrecurring engineering (NRE) costs. Reconfigurability is achieved with high number of point configuration memories which results in extreme application flexibility and, at the same time, significant overheads in area, performance, and power compared to Application Specific Integrated Circuits (ASIC) for the same functionality. In this thesis, we propose to design FPGAs with several 3D technologies for efficient FPGA circuits. First, we integrate resistive memory based blocks to reduce the routing wirelength and widen FPGA employability for low-power applications with non-volatile property. Among many technologies, we focus on Oxide Resistive Memory (OxRRAM) and Conductive Bridge Resistive Memory (CBRAM) devices by assessing unique properties of these technologies in circuit design. As another solution, we design a new FPGA with 3D monolithic integration (3DMI) by utilizing high-density interconnects. Starting from two layers with logic-on-memory approach, we examine various partitioning schemes with increased number of integrated active layers to reduce the routing complexity and increase logic density. Based on the obtained results, we demonstrate that multi-tier 3DMI is a strong alternative for future scaling.

The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible.

abstract: Non-volatile memory (NVM) has become a staple in the everyday life of consumers. NVM manifests inside cell phones, laptops, and most recently, wearable tech such as smart watches. NAND Flash has been an excellent solution to conditions requiring fast, compact NVM. Current technology nodes are nearing the physical limits of scaling, preventing flash from improving. To combat the limitations of flash and to appease consumer demand for progressively faster and denser NVM, new technologies are needed. One possible candidate for the replacement of NAND Flash is programmable metallization cells (PMC). PMC are a type of resistive memory, meaning that they do not rely on charge storage to maintain a logic state. Depending on their application, it is possible that devices containing NVM will be exposed to harsh radiation environments. As part of the process for developing a novel memory technology, it is important to characterize the effects irradiation has on the functionality of the devices. This thesis characterizes the effects that ionizing γ-ray irradiation has on the retention of the programmed resistive state of a PMC. The PMC devices tested used Ge30Se70 doped with Ag as the solid electrolyte layer and were fabricated by the thesis author in a Class 100 clean room. Individual device tiles were wire bonded into ceramic packages and tested in a biased and floating contact scenario. The first scenario presented shows that PMC devices are capable of retaining their programmed state up to the maximum exposed total ionizing dose (TID) of 3.1 Mrad(Si). In this first scenario, the contacts of the PMC devices were left floating during exposure. The second scenario tested shows that the PMC devices are capable of retaining their state until the maximum TID of 10.1 Mrad(Si) was reached. The contacts in the second scenario were biased, with a 50 mV read voltage applied to the anode contact. Analysis of the results show that Ge30Se70 PMC are ionizing radiation tolerant and can retain a programmed state to a higher TID than NAND Flash memory. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2015

abstract: This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2015

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

Resistive random access memory (RRAM), based on a two-terminal resistive switching device with a switching element sandwiched between two electrodes, has been an attractive candidate to replace flash memory owing to its simple structure, excellent scaling potential, low power consumption, high switching speed, and good retention and endurance properties. However, due to the current limited understanding of the device mechanism, RRAMs research are still facing several issues and challenges including instability of operation parameters, the relatively high reset current, the limited retention and the unsatisfactory endurance. In this study, we investigated the switching mechanisms, conditions and applications of oxygen vacancy (Vo) filament formation in resistive memories. By studying the behavior of conductive Vo nanofilaments in several metal/oxide/metal resistive devices of various thicknesses of oxides, a resulting model supported by the data postulates that there are two distinct modes of creating oxygen vacancies: i) a conventional bulk mode creation, and ii) surface mode of creating oxygen vacancies at the active metal-dielectric interface. A further investigation of conduction mechanism for the Vo CF only based memories is conducted through insertion of a thin layer of titanium into a Pt/ Ta2O5/Pt structure to form a Pt/Ti/ Ta2O5/Pt device. A space charge limited (SCL) conduction model is used to explain the experimental data regarding SET process at low voltage ranges. The evidence for existence of composite copper/oxygen vacancy nanofilaments is presented. The innovative use of hybrid Vo/Cu nanofilament will potentially overcome high forming voltage and gas accumulation issues. A resistive floating electrode device (RFED) is designed to allow the generation of current/voltage pulses that can be controlled by three independent technology parameters. Our recent research has demonstrated that in a Cu/TaOx/Pt resistive device multiple Cu conductive nanofilaments can be formed and ruptured successively. Near the end of the study, quantized and partial quantized conductance is observed at room temperature in metal-insulator-metal structures with graphene submicron-sized nanoplatelets embedded in a 3-hexylthiophene (P3HT) polymer layer. As an organic memory, the device exhibits reliable memory operation with an ON/OFF ratio of more than 10. / Ph. D.

Cette thèse s'inscrit dans le contexte de l'étude des circuits neuromorphiques utilisant des dispositifs memristifs comme synapses. Son objectif principal est d'évaluer les mérites d'une nouvelle classe de mémoires organiques développées au LICSEN (CEA Saclay/IRAMIS) et, plus particulièrement, leur adéquation avec les propositions d'implémentation et les règles d'apprentissage proposées par l'équipe NanoArchi de l'IEF (Univ. Paris-Sud, Orsay). Les memristors étudiés sont basés sur l'electro-greffage en films minces de complexes organiques redox pour la formation de jonctions métal/molécules/métal robustes et scalables. Outre la fabrication de memristors, le travail inclut d'importants efforts de caractérisation électrique (vitesse, non-volatilité, scalabilité, robustesse, etc.) visant d'une part à étudier les mécanismes de commutation dans ces nouveaux matériaux memristifs organiques, et d'autres part, à évaluer leur potentiel en tant que synapses. Cette thèse présente également une étude préparatoire à la réalisation d'un démonstrateur de circuit mixte de type réseaux de neurones combinant nano-memristors et électronique conventionnelle (programmabilité des dispositifs en mode impulsionnel, réalisation d'assemblées de dispositifs, variabilité). De plus, la démonstration de la compatibilité de ces memristors avec la propriété STDP (Spike Timing Dependent Plasticity) ainsi que de l’apprentissage d’un « réflexe conditionné » ouvrent la voie aux apprentissages non-supervisés. / This PhD project takes place in the context of the study of neuromorphic circuits using memristor devices as synapses. The main objective is to evaluate a new class of organic memories developed at LICSEN (CEA Saclay/IRAMIS) and particularly their compatibility with the learning rules and the implementation strategy proposed by the Nanoarchi group at IEF (Univ. Paris-Sud, Orsay). These new memristors are based on the electro-grafting of organic redox complexes thin films to form robust and scalable metal/molecules/metal junctions. In addition to memristor fabrication, this work includes detailed electrical characterization studies (speed, retention property, scalability, robustness, etc.) aiming at, on the one hand, establishing the commutation mechanism in these new memristors and, on the other hand, evaluating their potential as synapses. This work also proposes a preparatory study of a neural-network type mixed-circuit demonstrator combining nano-memristors and conventional electronic (programmability of devices by spikes, fabrication of assemblies of memristors, variability). Moreover the demonstration of the compatibility of such memristors with the STDP (Spike Timing Dependent Plasticity) property and of the learning of a “conditioned reflex” opens the way to future unsupervised learning studies.