In recent years, the fundamental researches on nanocrystals have been received increasing attentions for the novel applications, especially the nonvolatile memory technology. Adoption of nanocrystals technology could solve the serious limitation suffered by the conventional nonvolatile memory, flash, while scaling down. Once the thin tunneling oxide of flash device has been created a leaky path, all the stored charge in the floating gate will be lost after numerous counts of data reading and writing. Hence, the thinning of tunneling oxide will become one of important keys to the scaling limitation. Furthermore, if the tunneling oxide can not be thinned any more, both the operation voltage and speed of memory can not be improved. These drawbacks will restrict the development of nonvolatile memory. Replacement of floating gate structure with nanocrystals could effectively avoid the data losing due to the leaky path in the thin tunneling oxide. All stored charges can¡¦t be lost through the few leaky paths since the charges are stored in distributed nanocrystals. The charges stored nearby the leaky path will be lost, but others are still kept in the distributed and independent nanocrystals. The advantages of metal nanocrystals has have higher density of states around Fermi level, stronger coupling with conduction channel, wide range of available work functions and smaller energy perturbation due to carrier confinement. So metal nanocrystals can reduce operate voltage, and increase write/erase speed and endurance. In this thesis, we will study of cobalt and cobalt-silicide as the memory storage element. The nanocrystals were formed by high temperature oxidation or metal rapid thermal annealing with all kinds of conditions. And we analyze the effect of electron storage at metal nanocrystals by means of material and electrical analysis.

This thesis contains four parts. In the first part, we investigate the post treatment of low-temperature-deposited high dielectric constant (high-k) thin films to enhance their properties. The high-pressure oxygen (O2 and O2+UV light) is employed to improve the properties of low-temperature-deposited metal oxide dielectric films and interfacial layer. In this study, 13nm HfO2 thin films are deposited by sputtering method at room temperature. Then, the oxygen treatments with a high-pressure of 1500 psi at 150 ¢J are performed to replace the conventional high temperature annealing. According to the XPS analyses, integration area of the absorption peaks of O-Hf and O-Hf-Si bonding energies apparently raise and the quantity of oxygen in deposited thin films also increases from XPS measurement. In addition, the leakage current density of standard HfO2 film after O2 and O2+UV light treatments can be improved from 3.12¡Ñ10-6 A/cm2 to 6.27¡Ñ10-7 and 1.3¡Ñ10-8 A/cm2 at |Vg| = 3 V. The leakage current density is significantly suppressed and the current transport mechanism is transformed from trap-assisted tunneling to Schottky-Richardson emission due to the passivation of traps inside HfO2 film and interfacial layer. The proposed treatment is applicable for the future flexible electronics. In the second part of this thesis, we study the memory characteristics of CoSi2 nanocrystals with SiO2 or Al2O3/HfO2 multiple layer tunnel oxide. Due to the property of high-k, it can provide thicker physics thickness than thermal oxide (SiO2) under identical equivalent oxide thickness (EOT) and enhances the reliability without reducing the programming speed. By engineering the different dielectric constant materials and the energy band structure, the performance of nonvolatile memory can be improved. The device that employs HfO2/Al2O3/HfO2 as tunnel oxide exhibits better memory window and carrier injection efficiency than the device employing thermal oxide. Furthermore, the device employs Al2O3/HfO2/Al2O3 as tunnel oxide present the better retention characteristics than the device employs HfO2/Al2O3/HfO2 as tunnel oxide. The corresponding mechanisms were also discussed. For the advanced nonvolatile application, high-k material - hafnium oxide was applied on the resistance switching nonvolatile memory device as resistive switching layer with TiN/Ti/HfO2/TiN structure in the third part of this thesis. By using a thin Ti layer as the reactive buffer layer into the anode side, the proposed device exhibits superior bistable characteristics. Since the Ti can easily absorb oxygen atoms from buried HfO2, the TiN/Ti bi-layer can greatly improve the resistive switching characteristics. The mechanism of the proposed device is dominated by the redox reaction between the Hf and HfOX. In addition, the proposed device has multi-bit storage ability to enhance the storage density. From the temperature-dependent measurements, the low ambient temperatures would cause the formation and rupture of the conduction path with discordant quality and quantity during every switching cycle, which give rise to a wide distribution of the HRS and LRS resistance and instability of resistive switching properties. In the fourth part of this thesis, we investigate the characteristics of an advanced Cu-induced resistance switching non-volatile memory with Pt/Cu/SiON/TiN/SiO2/Si structure. By inserting a Cu ultra thin film between the SiON layer and Pt top electrode, the device exhibits bipolar resistive switching characteristics after a forming process at 13.6 V. However, the forming and resistive switching process can not be observed in the device if the Cu thin film is omitted. Additionally, we employ a two-step forming process to reduce the forming voltage to 7.5 V. During the forming process, the bias-induced Cu could form a filament-like stretched electrode, but the ¡§set¡¨ and ¡§forming¡¨ voltage of the proposed device take place on different polarity. Therefore, we suppose a bipolar switching mechanism, and our device is dominated by the formation and rupture of the oxygen vacancies in a conduction path between the Cu filament and TiN button electrode. The device also demonstrates stable resistance states during 105 cycling bias pulse operations and acceptable retention characteristics after an endurance test at 85¢J. The I-V switching curves are analyzed to realize the carrier transport mechanisms in different bias regions and resistance states. Additionally, the effective thickness of the resistance switching layers (deff) for the samples with different SiON thickness is also extracted from the related mechanism and demonstrated that the deff is independent with the initial SiON thickness. The corresponding mechanisms and the deff verify the bipolar switching is dominated by the formation and rupture of the oxygen vacancies in conduction path between Cu filament and TiN bottom electrode.

The advent of many core architectures has coincided with the energy and power limited design of modern processors. Projections for main memory clearly show widening of the processor-memory gap. Cache capacity increased to help reduce this gap will lead to increased energy and area usage and due to small growth in die size, impede performance scaling that has accompanied Moore's Law to date. Among the dominant sources of energy consumption is the on-chip memory hierar- chy, specically the L2 cache and the Last Level Cache (LLC). This work explores the use of a novel non-volatile memory technology - Spin Torque Transfer RAM (STT RAM)" for the design of the L2/LLC caches. While STTRAM is a promising memory technology, it has some limitations, particularly in terms of write energy and write latencies. The main objectives of this thesis is to use a novel cell design for a non-volatile 1T1MTJ cell and demonstrate its use at the L2 and LLC cache levels with architectural optimizations to maximize energy reduction. The proposed cache hierarchy dissipates significantly lesser energy (both leakage and dynamic) and uses less area in comparison to a conventional SRAM based cache designs.

abstract: Non-volatile memories (NVM) are widely used in modern electronic devices due to their non-volatility, low static power consumption and high storage density. While Flash memories are the dominant NVM technology, resistive memories such as phase change access memory (PRAM) and spin torque transfer random access memory (STT-MRAM) are gaining ground. All these technologies suffer from reliability degradation due to process variations, structural limits and material property shift. To address the reliability concerns of these NVM technologies, multi-level low cost solutions are proposed for each of them. My approach consists of first building a comprehensive error model. Next the error characteristics are exploited to develop low cost multi-level strategies to compensate for the errors. For instance, for NAND Flash memory, I first characterize errors due to threshold voltage variations as a function of the number of program/erase cycles. Next a flexible product code is designed to migrate to a stronger ECC scheme as program/erase cycles increases. An adaptive data refresh scheme is also proposed to improve memory reliability with low energy cost for applications with different data update frequencies. For PRAM, soft errors and hard errors models are built based on shifts in the resistance distributions. Next I developed a multi-level error control approach involving bit interleaving and subblock flipping at the architecture level, threshold resistance tuning at the circuit level and programming current profile tuning at the device level. This approach helped reduce the error rate significantly so that it was now sufficient to use a low cost ECC scheme to satisfy the memory reliability constraint. I also studied the reliability of a PRAM+DRAM hybrid memory system and analyzed the tradeoffs between memory performance, programming energy and lifetime. For STT-MRAM, I first developed an error model based on process variations. I developed a multi-level approach to reduce the error rates that consisted of increasing the W/L ratio of the access transistor, increasing the voltage difference across the memory cell and adjusting the current profile during write operation. This approach enabled use of a low cost BCH based ECC scheme to achieve very low block failure rates. / Dissertation/Thesis / Ph.D. Electrical Engineering 2014

There is an increased interest in the Conductive Bridge Random Access Memory (CBRAM) and Resistive Random Access Memory (RRAM) because of their excellent scaling potential, low power consumption, high switching speed, good retention and endurance properties. Although, various mechanisms have been proposed to explain the switching behavior in CBRAM devices, i.e. metal ion migration and subsequent formation and rupture of conductive filament, formation of conductive path via oxygen ion transport etc, there are still many aspects of these mechanisms that are little understood or are being disputed. This work probes the details of the switching mechanisms on a new level and asks questions like: 1) How is the formation of nanofilament affected by various degrees of Cu diffusion stopping power of the inert electrode? To answer this question, resistive switches with very thin Cu layers covering the Pt electrode were fabricated and analyzed. 2) How does a limited source of active ions impact the formation and rupture of nanofilaments? To answer this question, new samples with limited Cu supply were fabricated and analyzed. 3) What is the mechanism of nanofilament formation in Pt/TaOx/Pt resistive switches where the active copper electrode is removed and replaced by inert Pt electrode. 4) What are the most suitable conditions (material structure of the device and operation conditions) to set and reset multi nanofilaments? This work summarizes the current status of analysis of the data obtained while attempting to explain interesting phenomena like volatile switching and multiple filament formation experienced by modifying the switch structures. / Master of Science

Chalcogenide phase change (PC) materials can be reversibly transformed between the high resistivity (~ 1 Ω∙m) amorphous state (OFF-state) and low resistivity (~ 10-6 Ω∙m) crystalline state (ON-state) thermally, both are stable at the room temperature. This makes them well suited as reconfigurable RF switches and non-volatile memories. This work will present the understandings of two key characteristics of PC materials, the crystallization dynamics and the threshold voltage (Vth), as they determine performance limitations in these applications. Crystallization dynamics describe the correlations of the states, temperature and time; the Vth is the trigger of the threshold switching which leads to the “break down” of PC materials from OFF-state to ON-state. The four-terminal indirectly-heated RF switches with high cut-off frequency (> 5 THz) has advantages over other technologies but its programming power (~ 1.5 W) is yet to be reduced. Measuring the maximum allowed RESET quench time in the crystallization dynamics is critical for designing low power switches. As a major contribution, this work provides a universal methodology for accurate heater thermometry and in-situ crystallization measurements for this study. On the other hand, understanding the Vth is essential for high power handling applications as it determines the maximum power that an OFF-state switch can withstand without being spontaneously turned on. This work will discuss new observations and learnings from Vth measurements including the geometry dependent Vth variations which provide insights into the threshold switching mechanism. Unlike RF switches, faster crystallization is desired for memories to improve the write speed. The non-Arrhenius crystallization needs to be explored to achieve short crystallization time (< 10 ns) at high temperature (> 700 K). As another major contribution, this work will present a nano-scale (~ 100 nm) high-speed (thermal time constant < 5 ns) PC device for assessing the crystallization time in this regime, and provide a comprehensive learning for the crystallization dynamics from 300 K to 1000 K by developing a unified framework based on the fragility model and growth-dominated crystallization. This can be used to accurately simulate the crystallization process for any device geometry and estimate the RF switches power and Vth.

In the context of emerging non-volatile memory (NVM) where data structures can persist in-memory and are accessed through CPU loads and stores, we study how to efficiently manage data evolution. This is an extensively applied problem in both the scientific and business domains and is rapidly becoming an important component for a wider range of applications. We argue that the best way to achieve a smoother transition to the new programming model is to design a solution that is non-intrusive and generic i.e. not bound to a specific data model. We propose a novel library-level approach where the user can manage historical data directly from programming language code. This is achieved with a combination of two software layers: REWIND and VARIANT. At the bottom, lies REWIND (REcovery Write-Ahead System for In- Memory Non-Volatile Data Structures) which handles the low level specifics of NVM by dealing with write-ordering problems that arise in such context and allows recoverability of arbitrary data structures. Then, VARIANT (Versioning ARbItrary dAta structures in Non-volatile memory for Time-travel) focuses on versioning and time travel (moving between versions). We adopt a logging approach and we tightly integrate both systems for best performance by utilizing a common physical log of memory operations. With REWIND, we propose a novel recoverable log structure that permits atomic and durable appends and removals of log records. This is the keystone for building recoverable systems on top of NVM. Because latencies in recent NVM technologies such as Phase-change memory (PCM) are asymmetric, we propose novel techniques for reducing the write pressure of the recoverable log as well as mitigating the effect of synchronization control primitives such as memory fences (enhanced for NVM), i.e. barriers that enforce ordering and persistence to preceding instructions. We also propose different implementations for trading logging performance for rollback performance when this is appropriate. Finally, we revisit state-of-the-art recovery algorithms for the new context given the different latencies and synchronization control. Our results clearly indicate that current approaches for recoverability are ill-fitted for persisting data structures in the new context and it is possible to achieve low-overhead logging with customized mechanisms. Next, we focus on data evolution. We expose a simple API that allows versioning and time travel with minimal intrusiveness. We propose mechanisms for efficient and transparent cloning of Versionable data structures. This allows high concurrency since past images are returned as copies of the original data structure which remains intact. Then, we propose novel indexing techniques that significantly improve time travel performance as well as cloning with lazy schemes. We achieve a low overhead architecture by employing a mix of volatile and non-volatile data structures as well as hybrid structures that reside in both volatile and non-volatile memories. We perform an extensive evaluation of the proposed techniques and conclude that, in our context, by carefully mitigating the drawbacks of physical logging it is possible to create efficient systems for managing data evolution that are both data structure agnostic and non-intrusive.

Non-volatile memory is slower than DRAM (Dynamic Random Access Memory) but faster than HDD (Hard Disk Drive). In addition, compared to volatile memory, the non-volatile memory can retain stored information without power, and consume only low power. These characteristics show its popularity of flash memory built in portable devices. Currently the non-volatile memory applies the polysilicon and SONOS structure as floating gate, however, the new technologies of nanocrystal non-volatile memory are processed at high temperature. The manufacturing cost is rather high, so the process at lower temperature is very necessary. In this work, mixed zinc and silica amorphous layers are applied as floating gate to construct nano thin film non-volatile memory devices. The process does not need high temperature to form crystalline, and the defects in zinc oxide can be applied for charge storage. Supercritical carbon dioxide (SCCO2) treatment has been studied for the passivation of dielectric and reducing the activation energy. Using this low-temperature SCCD process ZnO nanocrystal can be formed, and the feasibility of fabricating nanocrystal NVMs device with low temperature SCCO2 is possible. The nonvolatile memory devices with Zn nano thin film embedded in MIS structure are performed. From C-V measurement, it is found that defects in SiO2 are repaired after 500¢J annealing. Because of the thermal diffusion, the storage layer SiO2/Zn-SiO2/SiO2 in device cannot be observed and the memory window disappears when the annealing temperature is higher than 700¢J. Therefore, the annealing process should be performed between 500¢J - 700¢J in making memory device. From DLTS analysis, a species with energy level of 0.6 eV is found in the as deposited Zn-SiO2 layer. After annealing in Ar, a new energy level 0.47 eV is found, and which shifts to energy level 0.85 eV after annealing in O2. In comparison to XPS results, traps of Zn-SiO2 exist before annealing, and after annealing in Ar, Zn-SiO2 transforms into Zn-O-Si. Traps of ZnO-SiO2 have been found after annealing in O2, which increases the memory effect with a 2 Volt memory window, so that more charges can be stored in the deep level traps of ZnO-SiO2 in the storage layer.

In recent years, due to the rapid development of electronic products, non-volatile memory has become more and more important. However, flash memory has faced some physical limits bottleneck with size scaling-down. In order to overcome this problem, alternative memory technologies have been extensively investigated, including ferroelectric random access memory (FeRAM), magneto resistive RAM (MRAM), phase-change RAM (PRAM), and resistive RAM (RRAM). All of this potential next generation non-volatile memory, the resistive random access memory has most advantages such as simple structure, lower consumption of energy, lower operating voltage, high operating speed, high storage time and non-destructive access, which make it be the most potential candidate of the next generation non-volatile memory. Many studies have proposed to explain the resistance switching phenomenon, which is due to the metallic filament or the oxygen vacancies. Therefore, in order to investigate the influence of resistance switching characteristic by metal or oxygen, we choose the non-metal contained boron oxy-nitride film as the insulator layer and successfully make the resistance has the switchable characteristic of this device. Furthermore, we improved the iv stability by using the Gadolinium-doped method in the boron oxy-nitride based film. In addition, we observed the negative current differential phenomenon during the set process, which can further controlled by lower operating voltage to achieve the interfacial resistance switching. We think that is due to the formation of nitrogen titanium oxide at the interface between insulator layer and titanium nitride electrode, which caused the Schottky barrier formation and reduced the current flow. In addition, current conduction fitting can also confirm this hypothesis. Besides, titanium nitride easily bond with oxygen ions; moreover, the oxygen ions can be easily disturbed at higher temperature ambient. We believed there may easily form the nitrogen titanium oxide layer in higher temperature environment; which also improve by a series of varied temperature experiments. However, this nitrogen titanium oxide layer formed naturally very easily, resulting in an inevitable problem of data retention time, which wish to be resolved in the future.

The operating characteristics of non-volatile memory for modern requirement are high-density , low power consumption, fast read and write speed, and good reliability. The floating gate memory generated leakage path in the tunnel oxide during the trend of scaling down, which will result in the loss of all stored charge to the silicon substrate. As the data retention time and endurance are taken into consideration, the thickness of tunnel oxide exist a physical limit, owing to the demand of high-density capacities. RRAM is offered as an option in the next generation non-volatile memories, due to the following advantages: (1) simple structure and easy to process, and low cost ; (2) less restrictive in the scaling-down process; (3) with the multi-bit data storage features; (4) high speed operation; (5) Repeat write and read is more than one million. In the thesis, we use a simple and low-temperature process to form the silicon germanium oxide (Si-Ge-O) RRAM and silicon germanium oxide RRAM with nitrogen doping between the electrode and silicon-germanium oxide interface. By sputtering at argon and oxygen (Ar/O2), and sputtering at argon and ammonia (Ar/NH3) with silicon-germanium target to form silicon germanium oxide RRAM and silicon germanium oxide (Si-Ge-O)/silicon germanium oxnitride (Si-Ge-O-N) RRAM. By informing a SiGeON layer between the interface of electrode and silicon-germanium oxide improve the stability of write voltage and endurance reliability. In addition, both silicon and germanium are useful as materials in the optoelectronics industry and extensively studied in material science. Based on the two materials, the smiting characterizations of RRAM will be improved in the read-write stability and operation reliability.