There is an increased interest in the Conductive Bridge Random Access Memory (CBRAM) and Resistive Random Access Memory (RRAM) because of their excellent scaling potential, low power consumption, high switching speed, good retention and endurance properties. Although, various mechanisms have been proposed to explain the switching behavior in CBRAM devices, i.e. metal ion migration and subsequent formation and rupture of conductive filament, formation of conductive path via oxygen ion transport etc, there are still many aspects of these mechanisms that are little understood or are being disputed. This work probes the details of the switching mechanisms on a new level and asks questions like: 1) How is the formation of nanofilament affected by various degrees of Cu diffusion stopping power of the inert electrode? To answer this question, resistive switches with very thin Cu layers covering the Pt electrode were fabricated and analyzed. 2) How does a limited source of active ions impact the formation and rupture of nanofilaments? To answer this question, new samples with limited Cu supply were fabricated and analyzed. 3) What is the mechanism of nanofilament formation in Pt/TaOx/Pt resistive switches where the active copper electrode is removed and replaced by inert Pt electrode. 4) What are the most suitable conditions (material structure of the device and operation conditions) to set and reset multi nanofilaments? This work summarizes the current status of analysis of the data obtained while attempting to explain interesting phenomena like volatile switching and multiple filament formation experienced by modifying the switch structures. / Master of Science

In an effort to lower interconnect time delays and power dissipation in highly integrated logic and memory nanoelectronic products, numerous changes in the materials and processes utilized to fabricate the interconnect have been made in the past decade. Chief among these changes has been the replacement of aluminum (Al) by copper (Cu) as the interconnect metal and the replacement of silicon dioxide (SiO2) by so called low dielectric constant (low-k) materials as the insulating interlayer dielectric (ILD). Cu/low-k structure significantly decreases the RC delay compared with the traditional interconnect (Al/SiO₂). Therefore, the implementation of low-k dielectric in Cu interconnect structures has become one of the key subjects in the microelectronics industry. Incorporation of pores into the existing low-k dielectric is a favorable approach to achieve ultra low-k ILD materials. To bring memory and logic closer together is an effective approach to remove the latency constraints in metal interconnects. The resistive random access memories (RRAM) technology can be integrated into a complementary metal-oxide-semiconductor (CMOS) metal interconnect structure using standard processes employed in back-end-of-line (BEOL) interconnect fabrication. Based on this premise, the study of this thesis aims at assessing a possible co-integration of resistive switching (RS) cells with current BEOL technology. In particular, the issue is whether RS can be realized with porous dielectrics, and if so, what is the electrical characterization of porous low-k/Cu interconnect-RS devices with varying percentages of porosity, and the diffusive and drift transport mechanism of Cu across the porous dielectric under high electric fields. This work addresses following three areas: 1. Suitability of porous dielectrics for resistive switching memory cells. The porous dielectrics of various porosity levels have been supplied for this work by Intel Inc. In course of the study, it has been found that Cu diffusion and Cu+ ion drift in porous materials can be significantly different from the corresponding properties in non-porous materials with the same material matrix. 2. Suitability of ruthenium as an inert electrode in resistive switching memory cells. Current state-of-the-art thin Cobalt (Co)/Tantalum Nitride (TaN) bilayer liner with physical vapor deposited (PVD) Cu-seed layer has been implemented for BEOL Cu/low-k interconnects. TaN is used for the barrier and Co is used to form the liner as well as promoting continuity for the Cu seed. Also, the feasibility of depositing thin CVD ruthenium (Ru) liners in BEOL metallization schemes has been evaluated. For this study, Ru is used as a liner instead of Ta or Co in BEOL interconnects to demonstrate whether it can be a potential candidate for replacing PVD-based TaN/Ta(Co)/Cu low-k technology. In this context, it is of interest to investigate how Ru would perform in well-characterized RS cell, like Cu/TaOx/Ru, given the fact that Cu/TaOx/Pt device have been proven to be good CBRAM device due to its excellent unipolar and bipolar switching characteristics, device performance, retention, reliability. If Cu/TaOx/Ru device displays satisfactory resistive switching behavior, Cu/porous low-k dielectric/Ru structure could be an excellent candidate as resistive switching memory above the logic circuits in the CMOS back-end. 3. Potential of so-called covalent dielectric materials for BEOL deployment and possibly as dielectric layer in the resistive switching cells. The BEOL reliability is tied to time dependent failure that occurs inside dielectric between metal lines. Assessing the suitability of covalent dielectrics for back-end metallization is therefore an interesting topic. TDDB measurements have been performed on pure covalent materials, low-k dielectric MIM and MI-semiconductor (MIS) devices supplied by Intel Inc. / Master of Science

Owing to its excellent scaling potential, low power consumption, high switching speed, and good retention, and endurance properties, Resistive Random Access Memory (RRAM) is one of the prime candidates to supplant current Nonvolatile Memory (NVM) based on the floating gate (FG) MOSFET transistor, which is at the end of its scaling capability. The RRAM technology comprises two subcategories: 1) the resistive phase change memory (PCM), which has been very recently deployed commercially, and 2) the filamentary conductive bridge RAM (CBRAM) which holds the promise of even better scaling potential, less power consumption, and faster access times. This thesis focuses on several aspects of the CBRAM technology. CBRAM devices are based on nanoionics transport and chemo-physical reactions to create filamentary conductive paths across a dielectric sandwiched between two metal electrodes. These nano-size filaments can be formed and ruptured reliably and repeatedly by application of appropriate voltages. Although, there exists a large body of literature on this topic, many aspects of the CBRAM mechanisms and are still poorly understood. In the next paragraph, the aspects of CBRAM studied in this thesis are spelled out in more detail. CBRAM cell is not only an attractive candidate for a memory cell but is also a good implementation of a new circuit element, called memristor, as postulated by Leon Chua. Basically, a memristor, is a resistor with a memory. Such an element holds the promise to mimic neurological switching of neuron and synapses in human brain that are much more efficient than the Neuman computer architecture with its current CMOS logic technology. A memristive circuitry can possibly lead to much more powerful neural computers in the future. In the course of the research undertaken in this thesis, many memristive properties of the resistive cells have been found and used in models to describe the behavior of the resistive switching devices. The research performed in this study has also an immediate commercial application. Currently, the semiconductor industry is faced with so-called latency scaling dilemma. In the past, the bottleneck for the signal propagation was the time delay of the transistor. Today, the transistors became so fast that the bottleneck for the signal propagation is now the RC time delay of the interconnecting metal lines. Scaling drives both, resistance and parasitic capacitance of the metal lines to very high values. In this context, one observes that resistive switching memory does not require a Si substrate. It is therefore an excellent candidate for its implementation as an o n-chip memory above the logic circuits in the CMOS back-end, thus making the signal paths between logic and memory extremely short. In the framework of a Semiconductor Research Corporation (SRC) project with Intel Corporation, this thesis investigated the breakdown and resistive switching properties of currently deployed low k interlayer dielectrics to understand the mechanisms and potential of different material choices for a realization of an RRAM memory to be implemented in the back-end of a CMOS process flow. / Master of Science