In order to meet demands for faster and more efficient data processing, modern microprocessors are being designed with lower voltage implementations. The processor voltage supply in future generation processors will decrease to 1.1 V ~ 1.8V. More devices will be packed on a single processor chip, and processors will operate at higher frequencies, beyond 1GHz. Therefore, microprocessors need aggressive power management. Future generation processors will draw current up to 50 A ~ 100 A [2]. These demands, in turn, will require special power supplies and Voltage Regulator Modules (VRMs) to provide lower voltages with higher currents and fast transient capabilities for microprocessors. This work presents several low-voltage high-current VRM technologies for future generation data processing, communication, and portable applications. The developed advanced VRMs with these new technologies have advantages over conventional ones in power density, efficiency, transient response, reliability, and cost. The multi-module interleaved quasi-square-wave VRM topology achieves a very fast transient response and a very high power density. This topology significantly reduces the filter inductance and capacitance, while having small output and input ripples. The analysis, design, and experimental verification for this new topology are presented in this work. The current sensing and current sharing techniques are developed with simple and cost-effective implementations. With this technique, traditional current transformers and sensing resistors are not required, and the inductance value, MOSFET on resistance and other parasitics have no effect on current sharing results. The design principles are developed and experimentally verified. A generalized approach and an extension of the novel current sharing control are presented in this work. The techniques for improving VRM light load efficiency are developed in this work. By utilizing the duty cycle signal, VRMs can be implemented with advanced power management functions to reduce further the power consumption at light loads to extend the battery-operation time in portable systems or to facilitate the compliance with various "energy star" ("green" power) requirements in office systems. Four improved approaches are presented and verified with experimental results. The high-input-voltage VRM topology, push-pull forward converter, can be used in high-bus-voltage distributed power systems. This converter has a high efficiency, a high power density, a fast transient response, and can be easily packaged as a standard module. The circuit design and experimental evaluation are addressed to demonstrate the operation principles and advantages of this topology. / Ph. D.

With the electronic equipments becoming more and more complicated, the requirements for the power management are more and more strict. Efficient performance, high functionality, small profile, fast transient and low cost are the most wanted features for modern power management ICs, especially for mobile power. In order to reduce profile, the number of external components should be as small as possible, which means that compensator, ramp compensation, current sensor, driver and even power devices should be all implemented on a single chip, i.e. monolithic integration. Comparing with discrete switching DC-DC converter, monolithic integration brings a number of benefits and new design challenges. Besides monolithic integration, high switching frequency is another trend for power management ICs due to its higher bandwidth and the ability to further reduce external passive component size. Comparing with low frequency counterparts, high frequency switching converter design is more difficult in terms of the stability modeling, high switching loss and difficult current sensing etc. The objective of this dissertation is to study the design issues for monolithic integration of high frequency switching DC-DC converter. For this purpose, a high frequency, wide input range monolithic buck converter ASIC with fast transient response is designed based on advanced trench BCD technology. Stability is the fundamental requirement in designing switching converter ASIC. Achieving this requires an accurate loop gain design, especially for monolithically integrated high frequency switching converter since compensator is fixed on silicon and loop delay is comparable with switching cycle. Since DC-DC switching converters are time-varying system, traditional small signal analysis in SPICE cannot be directly used to simulate the loop gain of this kind of system. A periodic small signal analysis based method is proposed to analyze and simulate DC-DC switching converter inside a SPICE like simulator without the need for averaging. This general method is suitable for any switching regulators. The results are accurate comparing with average modeling and experiment results even at high frequency part. A general procedure to design loop gain is proposed. Several novel design concepts are proposed for monolithic integration of high frequency switching DC-DC converter; a novel control scheme-Cotangent Control (Ctg control) is proposed for fast transient response; In order to realize on-chip implementation of the compensator, especially for low frequency zero, active feedback compensator is developed and a general design procedure is proposed. Adaptive compensation concept is proposed to stabilize the whole system for a wide application range. Multi-stage driver and multi-section device concepts are investigated for high efficiency and low noise power stage design. And finally, a new noise insensitive lossless RC sensor is proposed for high speed current sensing. At the end of this dissertation, the test results of the fabricated chip are presented to verify the correctness of these design concepts. / Ph. D.

Since the early 80s, the computer industry has undergone great expansion. Processors are becoming faster and more powerful. Power management issues in computing systems are becoming more and more complex and challenging. An evolution began when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. A so-called Voltage Regulator Module (VRM) is put close to the processor in order to provide the power as quickly as possible. Nowadays, for desktop and workstation applications, VRM input voltage has moved to the 12V output of the silver box. In the meantime, microprocessors will run at very low voltage (below 1V), will consume up to 100A of current, and will have dynamics of about 400A/us. In the near future, VRM will be replaced with VRD because of the parasitic components effect. The specifications requirements for VRD are even more challenging than VRM. With this kind of tight tolerance, high current and fast current slew rate, transient response requirements for VRD design are very challenging, especially for step-down transient. During step-down transient, there is some additional energy stored in inductor. Traditional switching regulator like multi-phase buck can do nothing for this even by saturating the duty cycle to 0. All of the additional energy in inductor will be dumped into output cap and cause a large voltage spike at the output voltage. Even for step-up transient, traditional linear control like voltage loop control can't provide enough bandwidth because of the slow compensation and slow slew rate of the error amplifier. So the voltage drop is still quite large. Comparing with traditional linear controlled switching regulator such as voltage control and current control buck converter, active clamp has a lot of the advantages for the transient response. With proper design, active clamp can generate a very high bandwidth since there is no compensator needed in the control loop. Since active clamp bypasses inductor and is connected directly to the output cap, it can quickly source and sink current from the output cap even during the step-down transient and prevent overshooting of the output voltage. This is the biggest advantage for active clamp comparing with traditional linear control. In this thesis, a new active clamp structure is proposed. Several new concepts are proposed like non-linear Gm, built-in offset Gm, error signal feedback and AVP design. A one-channel buck converter with new active clamp and voltage loop control is implemented and verified using real transistors based on 0.5um CMOS process. / Master of Science

As a scalable, high-efficiency, and simple converter topology, an interleaved, multiphase buck converter has been widely used to power microprocessors in information industry. As modern microprocessors continuously advance, the required current for high-performance microprocessors used in data center applications could be several hundreds of amperes with a current slew rate larger than 1000 A/μs. This poses great challenges for a high-efficiency, high-power-density voltage regulator design with a fast transient response. On the other hand, the design challenges of voltage regulators in mobile applications are also increasing due to the stringent requirement on the device thickness and the battery life. In a multiphase buck converter, discrete inductors are widely used as energy storage elements. However, this solution has a limited transient response with a large size of magnetic components. To overcome these issues, coupled inductor is proposed to realize a small steady-state current ripple, a fast transient response, and a small inductor size at the same time. Although lots of studies have been conducted in the topic of the coupled inductor, there are still several challenges unsolved in this area. These challenges are addressed through a comprehensive study in this dissertation. First, a comprehensive analysis of different coupled inductor structures is crucial to identify the benefits and limitations of each inductor structure and provide design guidance under different application requirements. Based on the coupling mechanism, different coupled inductor structures are categorized as a direct-coupled inductor (DCL), an indirect-coupled inductor (ICL) or a hybrid-coupled inductor (HCL) in this work. The performance of these three types of coupled inductors is analyzed in detail through the equivalent inductance analysis and the magnetic flux analysis. For the applications that require a small phase number, a DCL can achieve the smallest inductor size with a given inductance requirement. As the phase number increases, it is beneficial to use an ICL and an HCL due to their symmetrical, simple, and scalable inductor structures. As compared to an ICL, an HCL can achieve a smaller inductor size due to the flux-cancellation effect. The difference between a DCL, an ICL and an HCL are revealed quantitively with several design examples through this study. Second, the steady-state inductance (Lss) and the transient inductance (Ltr) are two key design parameters for coupled inductors. A large Lss and a small Ltr are preferred from the circuit performance point of view. However, there is a design conflict in an ICL and an HCL under the inductor size constraint, where reducing Ltr also results in a smaller Lss. A variable coupling coefficient concept is proposed to overcome this issue. With the same Lss, the proposed method can achieve a smaller Ltr during load transients as compared with the conventional method. This concept is realized by applying a nonlinear inductor in the additional winding loop with the current in this loop as the control source. Compared with the conventional structure, the proposed structure can achieve a great output voltage spike reduction and output capacitance reduction. Third, although an ICL and an HCL are promising candidates for multiphase coupled inductors, an extra inductor is required in the additional winding loop to adjust the coupling coefficient. This additional inductor occupies extra space. To shrink the total inductor size, several improved magnetic core structures are proposed to achieve the controllable coupling through the magnetic integration for an ICL and an HCL. Furthermore, the thickness of the core plate can be significantly reduced by the improved core structure for an HCL. Overall, it is demonstrated that the inductor footprint is greatly reduced by the proposed core structure, as compared with the conventional solution. Lastly, a novel PCB-embedded coupled inductor structure is proposed for a 20MHz integrated voltage regulator (IVR) for mobile applications. To achieve a small inductor footprint and a low profile, the inductor structure with a lateral flux pattern and direct coupling is adopted. Compared with the state-of-the-art solution, the proposed structure can adjust the coupling in a simple core structure by changing the inductor winding pattern. The proposed structure integrates multiple inductors into one magnetic core and is embedded into PCB with a total thickness of 0.54 mm. In contrast to prior arts, the proposed inductor structure features a large inductance density and quality factor with a much smaller DC resistance (DCR), thus is seen as a promising candidate for IVR applications. / Doctor of Philosophy / As modern microprocessors continuously advance in the information industry, the required current for high-performance microprocessors used in data center applications could be several hundreds of amperes with a current slew rate larger than 1000 A/μs. This poses great challenges for the power converter design. On the other hand, the design challenges of power converters in mobile applications are also increasing due to the stringent requirement on the device thickness and the battery life. As a scalable, high-efficiency, and simple converter topology, an interleaved, multiphase buck converter has been widely used to power these processors. In a multiphase buck converter, discrete inductors are widely used as energy storage elements. However, this solution has a limited transient response with a large size of magnetic components. To overcome these issues, coupled inductor is proposed to realize a small steady-state current ripple, a fast transient response, and a small inductor size at the same time. Although lots of studies have been conducted in the topic of the coupled inductor, there are still several challenges unsolved in this area. These challenges are addressed through a comprehensive study in this dissertation. First, a comprehensive analysis and comparison of different coupled inductor structures is crucial to identify the benefits and limitations of each inductor structure and provide design guidance under different application requirements. Based on the coupling mechanism, different coupled inductor structures are categorized as a direct-coupled inductor (DCL), an indirect-coupled inductor (ICL) or a hybrid-coupled inductor (HCL) in this work. The performance of these three types of coupled inductors is analyzed in detail through the equivalent inductance analysis and the magnetic flux analysis. The difference between a DCL, an ICL and an HCL are revealed quantitively with several design examples through this study. Second, the steady-state inductance (Lss) and the transient inductance (Ltr) are two key design parameters for coupled inductors. A large Lss and a small Ltr are preferred from the circuit performance point of view. However, there is a design conflict in an ICL and an HCL under the inductor size constraint, where reducing Ltr also results in a smaller Lss. A variable coupling coefficient concept is proposed to overcome this issue. This concept is realized by applying a nonlinear inductor in the conventional structure. Compared with the conventional structure, the proposed structure can achieve a great output voltage spike reduction and output capacitance reduction. Third, although an ICL and an HCL are promising candidates for multiphase coupled inductors, an extra inductor is required in the additional winding loop to adjust the coupling coefficient. This additional inductor occupies extra space. To shrink the total inductor size, several improved magnetic core structures are proposed to achieve the controllable coupling through the magnetic integration for an ICL and an HCL. Lastly, a novel PCB-embedded coupled inductor structure is proposed for a 20MHz integrated voltage regulator (IVR) for mobile applications. Compared with the state-of-the-art solution, the proposed structure can adjust the coupling in a simple core structure by changing the inductor winding pattern. In contrast to prior arts, the proposed inductor structure features a large inductance density and quality factor with a much smaller DC resistance (DCR), thus is seen as a promising candidate for IVR applications.

abstract: The increased adoption of Internet-of-Things (IoT) for various applications like smart home, industrial automation, connected vehicles, medical instrumentation, etc. has resulted in a large scale distributed network of sensors, accompanied by their power supply regulator modules, control and data transfer circuitry. Depending on the application, the sensor location can be virtually anywhere and therefore they are typically powered by a localized battery. To ensure long battery-life without replacement, the power consumption of the sensor nodes, the supply regulator and, control and data transmission unit, needs to be very low. Reduction in power consumption in the sensor, control and data transmission is typically done by duty-cycled operation such that they are on periodically only for short bursts of time or turn on only based on a trigger event and are otherwise powered down. These approaches reduce their power consumption significantly and therefore the overall system power is dominated by the consumption in the always-on supply regulator. Besides having low power consumption, supply regulators for such IoT systems also need to have fast transient response to load current changes during a duty-cycled operation. Supply regulation using low quiescent current low dropout (LDO) regulators helps in extending the battery life of such power aware always-on applications with very long standby time. To serve as a supply regulator for such applications, a 1.24 µA quiescent current NMOS low dropout (LDO) is presented in this dissertation. This LDO uses a hybrid bias current generator (HBCG) to boost its bias current and improve the transient response. A scalable bias-current error amplifier with an on-demand buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. Switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA for a low-ESR output capacitor range of 1 - 47µF. Designed in a 0.25 µm CMOS process, the LDO has an output voltage range of 1V – 3V, a dropout voltage of 240 mV, and a core area of 0.11 mm2. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

abstract: The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task. The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.

The main goal of this thesis is to develop practical digital controller architectures for multi-phase dc-dc converters utilized in low power (up to few hundred watts) and cost-sensitive applications. The proposed controllers are suitable for on-chip integration while being capable of providing advanced features, such as dynamic efficiency optimization, inductor current estimation, converter component identification, as well as combined dynamic current sharing and fast transient response. The first part of this thesis addresses challenges related to the practical implementation of digital controllers for low-power multi-phase dc-dc converters. As a possible solution, a multi-use high-frequency digital PWM controller IC that can regulate up to four switching converters (either interleaved or standalone) is presented. Due to its configurability, low current consumption (90.25 μA/MHz per phase), fault-tolerant work, and ability to operate at high switching frequencies (programmable, up to 10 MHz), the IC is suitable to control various dc-dc converters. The applications range from dc-dc converters used in miniature battery-powered electronic devices consuming a fraction of watt to multi-phase dedicated supplies for communication systems, consuming hundreds of watts. A controller for multi-phase converters with unequal current sharing is introduced and an efficiency optimization method based on logarithmic current sharing is proposed in the second part. By forcing converters to operate at their peak efficiencies and dynamically adjusting the number of active converter phases based on the output load current, a significant improvement in efficiency over the full range of operation is obtained (up to 25%). The stability and inductor current transition problems related to this mode of operation are also resolved. At last, two reconfigurable digital controller architectures with multi-parameter estimation are introduced. Both controllers eliminate the need for external analog current/temperature sensing circuits by accurately estimating phase inductor currents and identifying critical phase parameters such as equivalent resistances, inductances and output capacitance. A sensorless non-linear, average current-mode controller is introduced to provide fast transient response (under 5 μs), small voltage deviation and dynamic current sharing with multi-phase converters. To equalize the thermal stress of phase components, a conduction loss-based current sharing scheme is proposed and implemented.