This dissertation develops a modeling and simulation methodology for design, verification, and testing (DVT) power supply system using a virtual prototype. The virtual prototype is implemented before the hardware prototyping to detect most of the design errors and circuit deficiencies that occur in the later stage of a standard hardware design verification and testing procedure. The design iterations and product cost are reduced significantly by using this approach. The proposed modeling and simulation methodology consists of four major parts: system partitioning, multi-level modeling of device/function block, hierarchical test sequence, and multi-level simulation. By applying the proposed methodology, the designer can use the virtual prototype effectively by keeping a short simulation CPU time as well as catching most of the design problems. The proposed virtual prototype DVT procedure is demonstrated by simulating a 5 V power supply system with a main power supply, a bias power supply, and other protection, monitoring circuitry. The total CPU time is about 8 hours for 780 tests that include the basic function test, steady stage analysis, small-signal stability analysis, large-signal transient analysis, subsystem interaction test, and system interaction test. By comparing the simulation results with the measurements, it shows that the virtual prototype can represent the important behavior of the power supply system accurately. Since the proposed virtual prototype DVT procedure verifies the circuit design with different types of the tests over different line and load conditions, many circuit problems that are not obvious in the original circuit design can be detected by the simulation. The developed virtual prototype DVT procedure is not only capable of detecting most of the design errors, but also plays an important role in design modifications. This dissertation also demonstrates how to analyze the anomalies of the forward converter with active-clamp reset circuit extensively and facilitate the design and improve the circuit performances by utilizing the virtual prototype. With the help of the virtual prototype, it is the first time that the designer is able to analyze the dynamic behavior of the active-clamp forward converter during large-signal transient and optimize the design correspondingly. / Ph. D.

Since the early 80s, the computer industry has undergone great expansion. Processors are becoming faster and more powerful. Power management issues in computing systems are becoming more complex and challenging. An evolution began when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. A so-called Voltage Regulator Module (VRM), is put close to the processor in order to provide the power as quickly as possible. Nowadays, for desktop and workstation applications, VRM input voltage has moved to the 12V output of the silver box. In the meantime, microprocessors will run at very low voltage (below 1V), will consume up to 100A of current, and will have dynamics of about 400A/us. This work presents an investigation of three 12V VRM topologies: the synchronous buck converter, the tapped-inductor buck converter and the active-clamp couple-buck converter. The limitations of today¡¯s synchronous buck approach are identified. The extreme duty cycle of the current topology makes it difficult to design an efficient VRM with decent transient response. The tapped-inductor buck and the active-clamp couple-buck converters are discussed as solutions. The transient response and efficiency of each type of converter are compared. Ripple cancellation is also addressed. The analytical and experimental results are presented: The tapped-inductor buck can improve the efficiency, but suffers a voltage spike, which nullifies its candidacy; the active-clamp couple-buck converter can improve the efficiency while maintaining good transient response, and it is therefore a good candidate for 12V VRMs. / Master of Science

Since the early 80s, the computer industry has undergone great expansion. Processors are becoming faster and more powerful. Power management issues in computing systems are becoming more and more complex and challenging. An evolution began when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. A so-called Voltage Regulator Module (VRM) is put close to the processor in order to provide the power as quickly as possible. Nowadays, for desktop and workstation applications, VRM input voltage has moved to the 12V output of the silver box. In the meantime, microprocessors will run at very low voltage (below 1V), will consume up to 100A of current, and will have dynamics of about 400A/us. In the near future, VRM will be replaced with VRD because of the parasitic components effect. The specifications requirements for VRD are even more challenging than VRM. With this kind of tight tolerance, high current and fast current slew rate, transient response requirements for VRD design are very challenging, especially for step-down transient. During step-down transient, there is some additional energy stored in inductor. Traditional switching regulator like multi-phase buck can do nothing for this even by saturating the duty cycle to 0. All of the additional energy in inductor will be dumped into output cap and cause a large voltage spike at the output voltage. Even for step-up transient, traditional linear control like voltage loop control can't provide enough bandwidth because of the slow compensation and slow slew rate of the error amplifier. So the voltage drop is still quite large. Comparing with traditional linear controlled switching regulator such as voltage control and current control buck converter, active clamp has a lot of the advantages for the transient response. With proper design, active clamp can generate a very high bandwidth since there is no compensator needed in the control loop. Since active clamp bypasses inductor and is connected directly to the output cap, it can quickly source and sink current from the output cap even during the step-down transient and prevent overshooting of the output voltage. This is the biggest advantage for active clamp comparing with traditional linear control. In this thesis, a new active clamp structure is proposed. Several new concepts are proposed like non-linear Gm, built-in offset Gm, error signal feedback and AVP design. A one-channel buck converter with new active clamp and voltage loop control is implemented and verified using real transistors based on 0.5um CMOS process. / Master of Science

The bi-directional dc/dc converter is a very popular and effective tool for alternative energy applications. One way it can be utilized is to charge and discharge batteries used in residential solar energy systems. In the day, excess power from the PV panels is used to charge the batteries. During the night, the charged batteries will power the dc bus for loads in the house such as home appliances. The dual active bridge (DAB) converter is very useful because of its high power capability and efficiency. Its symmetry is effective in transferring power in both directions. However, the DAB converter has drawbacks in the start-up stage. These drawbacks in boost mode include high in-rush current during start-up, and the fact that the high side voltage cannot be lower than the low side voltage. A popular existing method to alleviate this problem is the use of an active clamp and a flyback transformer in the circuit topology to charge the high side before the converter is switched into normal boost operation. The active clamp not only helps eliminate the transient spike caused by the transformer leakage, but also continues to be used during steady state. However, this method introduces a new current spike occurring when the converter transitions from start-up mode to boost mode. To alleviate this new setback, an additional transitional stage is proposed to significantly reduce the current spike without the use of any additional components. The converter is current-fed on the low side, and voltage-fed on the high side. A simple phase shift control is used in buck mode and PWM control is used during the boost mode for both the start-up mode and the normal boost operation. This thesis discusses the performance results of a 48-400 V dc/dc converter with 1000 W power output. / Master of Science

In this thesis / analysis, design and implementation of a DC-DC converter with active clamp forward topology is presented. The main objective of this thesis is generating a rectified sinusoidal voltage at the output of the converter. This is accomplished by changing the reference signal of the converter. The converter output is applied to an inverter circuit in order to obtain sinusoidal waveform. The zero crossing points of the converter is detected and the inverter drive signals are generated in order to obtain sinusoidal waveform from the output of the converter. Next, the operation of the DC-DC converter and sinusoidal output inverter coupled performance is investigated with resistive and inductive loads to find out how the proposed topology performs. The design is implemented with an experimental set-up and steady state and dynamic performance of the designed power supply is tested. Finally an evaluation of how better performance can be obtained from this kind of arrangement to obtain a sinusoidal output inverted is thoroughly discussed

This thesis presents an active clamp forward converter for use in the Energy Harvesting From Exercise Machines project. Ideally, this converter will find use as the centerpiece in a process that links elliptical trainers to the California grid. This active clamp forward converter boasts a 14V-60V input voltage range and 150W power rating, which closely match the output voltage and power levels from the elliptical trainer. The isolated topology outputs 51V, higher than previous, non-isolated attempts, which allows the elliptical trainers to interact with a central grid-tied inverter instead of many small ones. The final converter operated at greater than 86% efficiency over most of the elliptical trainer’s input range, and produced very little noise, making it a solid choice for this implementation.

Switched mode power supplies (SMPS) have found wide spread acceptance in all power processing applications. The design demand is moving towards higher power densities. For reduction in size and weight, it is imperative to process the power at a higher switching frequency. High switching frequency requires soft switching techniques to reduce the switching losses. Several families of soft switching converters have emerged in the past two decades. Analysis and modelling methods have been proposed in relation with these topologies. Active clamp converters are the recently introduced soft switching topologies. Steady state analysis and model of these converters have been reported in literature. This thesis presents a unified equivalent circuit oriented model for the family of active clamp converters. Analytical expressions for DC conversion ratio in terms of pole current and throw voltage are derived for all the DC-DC converters with active clamp. The special feature is that, the conversion ratio exhibits a load dependent drop (IRd), where I is the pole current and Rd is the damping resistance. The damping resistance Rd is a mathematical artifact to represent the voltage loss on account of delay in the turn-on of the active switch. There is no energy loss associated with this load dependent drop. This is conveniently expressed as an appropriate lossless resistance in the equivalent circuit model. The proposed equivalent circuit models are valid for both steady-state and dynamic performance. A spread sheet based design is presented for the basic DC-DC converters with active clamp. A prototype design following the spreadsheet is made. The performance of the same is validated and verified by simulation and measurements. Steady state and dynamic results are presented. The stability criterion for the active clamp converters under current programming is investigated. The same is verified through simulation and validated on a current programmed active clamp converter prototype. The active clamp converters suffer from a few disadvantages: Higher VA ratings of switches, load dependent ZVS performance and increased component count. Several soft switching topologies have been reported in literature. Efficiency improvement and increase in switching frequency are obtained to different degrees. This thesis proposes a new family of soft switching converters. This family of converters switch at constant frequency and maintains the advantages of traditional PWM converters. The proposed topology employs an auxiliary circuit to achieve soft switching. The auxiliary circuit consists of a dependent voltage source, an auxiliary switch, a series diode and a set of resonant elements (Inductor and capacitor). The switching transitions of both the active switch and the auxiliary switch are lossless. The novelty in the proposed circuit is the method of generating the dependent source required to enable zero current switching of the auxiliary switch. The dependent source is realized by a coupled winding in the energy storage inductor or tapped from the energy transfer transformer of non-isolated and isolated converters respectively. The proposed topology is applicable to most of the isolated and non-isolated DC-DC converters. The circuit equations governing the sub-intervals of the converter are expressed in terms of pole current and throw voltage. With such a definition, performance results and the design equations are identical for all types of DC-DC converters. Equivalent circuit models are obtained for the whole family of DC-DC converters. The proposed model is valid for steady state and dynamic performance. Analytical expressions of DC conversion ratio for all topologies, in terms of pole current and throw voltage are derived. The special feature is that, the conversion ratio exhibits a load dependent drop (IRd), where I is the pole current and Rd is the damping resistance. The damping resistance Rd is a mathematical artifact to represent the voltage loss on account of delay in the turn-on of the active switch. There is no energy loss associated with this load dependent drop. This is conveniently expressed as an appropriate lossless resistance in the equivalent circuit model. Design guidelines are established for the whole family of proposed converters; the same are validated through prototype converters.