Since the early 80s, the computer industry has undergone great expansion. Processors are becoming faster and more powerful. Power management issues in computing systems are becoming more complex and challenging. An evolution began when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. A so-called Voltage Regulator Module (VRM), is put close to the processor in order to provide the power as quickly as possible. Nowadays, for desktop and workstation applications, VRM input voltage has moved to the 12V output of the silver box. In the meantime, microprocessors will run at very low voltage (below 1V), will consume up to 100A of current, and will have dynamics of about 400A/us. This work presents an investigation of three 12V VRM topologies: the synchronous buck converter, the tapped-inductor buck converter and the active-clamp couple-buck converter. The limitations of today¡¯s synchronous buck approach are identified. The extreme duty cycle of the current topology makes it difficult to design an efficient VRM with decent transient response. The tapped-inductor buck and the active-clamp couple-buck converters are discussed as solutions. The transient response and efficiency of each type of converter are compared. Ripple cancellation is also addressed. The analytical and experimental results are presented: The tapped-inductor buck can improve the efficiency, but suffers a voltage spike, which nullifies its candidacy; the active-clamp couple-buck converter can improve the efficiency while maintaining good transient response, and it is therefore a good candidate for 12V VRMs. / Master of Science

In the Nicomachean Ethics, Aristotle identifies three conditions that are necessary in order for a virtuous act to have been done as a virtuous agent: the act must be done (1) knowingly, (2) for itself, and (3) from a steady disposition. I examine previous interpretations of the second item, and then offer my own: a virtuous act is chosen for itself if it is chosen for its virtue-making features that are also reasons to do the act, and these features motivate the agent to such an extent that the agent would do the act even if there were no other reason to do it. / text

This dissertation describes the development of voltage regulators for the purpose of power reduction and further scaling in highly integrated system-on-chip products. Emphasis is placed on the architecture and implementation of integrated voltage regulation using commercially available components, standard CMOS technology, and a practical controller. The research spans the fundamental elements, architectural aspects, and detailed analog integrated circuit design. / text

Zugl.: Kiel, Univ., erw. Magisterarbeit, 2008 u.d.T.: Pauls, Torben : Das Verhältnis von Hermeneutik und Bildung bei Günther Buck.

Boston University. University Professors Program Senior theses. / PLEASE NOTE: Boston University Libraries did not receive an Authorization To Manage form for this thesis. It is therefore not openly accessible, though it may be available by request. If you are the author or principal advisor of this work and would like to request open access for it, please contact us at open-help@bu.edu. Thank you. / 2031-01-02

Multiphase interleaving buck converters are widely used in today's industrial point-of-load (POL) converters, especially the microprocessor voltage regulators (VRs). The issue of today's multiphase interleaving buck converters is the conflict between the high efficiency and the fast transient in the phase inductor design. In 2000, P. Wong proposed the multiphase coupledinductor buck converter to solve this issue. With the phase inductors coupled together, the coupled-inductor worked as a nonlinear inductor due to the phase-shifted switching network, and the coupled-inductor has different equivalent inductances during steady-state and transient. One the one hand, the steady state inductance is increased due to coupling and the efficiency of the multiphase coupled-inductor buck converter is increased; on the other hand, the transient inductance is reduced and the transient performance of the multiphase coupled-inductor buck is improved. After that, many researches have investigated the multiphase coupled-inductor buck converters in different aspects. However, there are still many challenges in this area: the comprehensive analysis of the converter, the alternative coupled inductor structures with the good performance, the current sensing of converter and the light-load efficiency improvement. They are investigated in this dissertation. The comprehensive analysis of the multiphase coupled-inductor buck converter is investigated. The n-phase (n>2) coupled-inductor buck converter with the duty cycle D>1/n hasn't been analyzed before. In this dissertation, the multiphase coupled-inductor buck converter is systematically analyzed for any phase number and any duty cycle condition. The asymmetric multiphase coupled-inductor buck converter is also analyzed. The existing coupled-inductor has a long winding path issue. In low-voltage, high-current applications, the short winding path is preferred because the winding loss dominates the inductor total loss and a short winding path can greatly reduce the winding loss. To solve this long winding path issue, several twisted-core coupled-inductors are proposed. The twisted-core coupled-inductor has such a severe 3D fringing effect that the conventional reluctance modeling method gives a poor result, unacceptable from the design point of view. By applying and extending Sullivan's space cutting method to the twisted core coupled inductor, a precise reluctance model of the twisted-core coupled-inductor is proposed. The reluctance model gives designers the intuition of the twisted-core coupled-inductors and facilitates the design of the twisted-core coupled-inductors. The design using this reluctance model shows good correlation between the design requirement and the design result. The developed space cutting method can also be used in other complex magnetic structures with the strong fringing effect. Today, more and more POL converters are integrated and the bottleneck of the integrated POL converters is the large inductor size. Different coupled-inductor structures are proposed to reduce the large inductor size and to improve the power density of the integrated POL converter. The investigation is based on the low temperature co-fire ceramic (LTCC) process. It is found that the side-by-side-winding coupled-inductor structure achieves a smaller footprint and size. With the two-segment B-H curve approximation, the proposed coupled-inductor structure can be easily modeled and designed. The designed coupled-inductor prototype reduces the magnetic size by half. Accordingly, the LTCC integrated coupled-inductor POL converter doubles the power density compared to its non-coupled-inductor POL counterpart and an amazing 500W/in³ power density is achieved. In a multiphase coupled-inductor converter, there are several coupled-inductor setups. For example, for a six-phase coupled-inductor converter, three two-phase coupled inductors, two three-phase coupled-inductors and one six-phase coupled inductors can be used. Different coupled-inductor setups are investigated and it is found that there is a diminishing return effect for both the steady-state efficiency improvement and the transient performance improvement when the coupling phase number increases. The conventional DCR current sensing method is a very popular current sensing method for today's multiphase non-coupled-inductor buck converters. Unfortunately, this current sensing method doesn't work for the multiphase coupled-inductor buck converter. To solve this issue, two novel DCR current sensing methods are proposed for the multiphase coupled-inductor buck converter. Although the multiphase coupled-inductor buck converters have shown a lot of benefits, they have a low efficiency under light-load working in DCM. Since the DCM operation of the multiphase coupled-inductor buck converter has never been investigated, they are analyzed in detail and the reason for the low efficiency is identified. It is found that there are more-than-one DCM modes for the multiphase coupled-inductor buck converter: DCM1, DCM2 …, and DCMn. In the DCM2, DCM3 …, and DCMn modes, the phase-currents reach zero-current more-than-once during one switching period, which causes the low efficiency of the multiphase coupledinductor buck converter in the light load. With the understanding of the low efficiency issue, the burst-in-DCM1-mode control method is proposed to improve the light load efficiency of the multiphase coupled-inductor buck converter. Experimental results prove the proposed solution. / Ph. D.

abstract: Synchronous buck converters have become the obvious choice of design for high efficiency voltage down-conversion applications and find wide scale usage in today's IC industry. The use of digital control in synchronous buck converters is becoming increasingly popular because of its associated advantages over traditional analog counterparts in terms of design flexibility, reduced use of off-chip components, and better programmability to enable advanced controls. They also demonstrate better immunity to noise, enhances tolerance to the process, voltage and temperature (PVT) variations, low chip area and as a result low cost. It enables processing in digital domain requiring a need of analog-digital interfacing circuit viz. Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC). A Digital to Pulse Width Modulator (DPWM) acts as time domain DAC required in the control loop to modulate the ON time of the Power-MOSFETs. The accuracy and efficiency of the DPWM creates the upper limit to the steady state voltage ripple of the DC - DC converter and efficiency in low load conditions. This thesis discusses the prevalent architectures for DPWM in switched mode DC - DC converters. The design of a Hybrid DPWM is presented. The DPWM is 9-bit accurate and is targeted for a Synchronous Buck Converter with a switching frequency of 1.0 MHz. The design supports low power mode(s) for the buck converter in the Pulse Frequency Modulation (PFM) mode as well as other fail-safe features. The design implementation is digital centric making it robust across PVT variations and portable to lower technology nodes. Key target of the design is to reduce design time. The design is tested across large Process (+/- 3σ), Voltage (1.8V +/- 10%) and Temperature (-55.0 °C to 125 °C) and is in the process of tape-out. / Dissertation/Thesis / M.S. Electrical Engineering 2013

Buck converter is a power converter which drops high input voltage into a low output voltage in high efficiency. With this characteristic, it has been used in a great number of applications. Optimized the maximum load to increase the buck converter's efficiency at the cost of light load efficiency is a general way used in a traditional buck converter because it has a higher impact on power consumption. We propose a novel way of designing the two-phase buck converter with light load efficiency improvement in this thesis. The purposed two-phase buck converter uses RC delay to control switch frequency. Different frequency will affect the buck converter in output value and efficiency. RC delay includes two parts; part one connect with phase one, part two connect with phase two. After the test, when resister's value of part one is 100kΩ, and the capacitor's value is 50 pF, the resister's value of path two is 40kΩ, and the capacitors' value is 50 pF, the buck converter can reach maximum efficiency. The inspiration of the neural network is derived from the biological brain, neural is similar with the human neural, and the synaptic weights can treat as the connection between two nodes. Reservoir computing can be seen as an extension of the neural network since it is a framework for computation. Echo State Network(ESN) is one of the major types of reservoir computing, and it is a recurrent neural network. Compared with a neural network, it only trains output weights, which can save a lot of time but keep the accuracy of the training at the same time. The efficiency of the two-phase buck converter and power loss for each phase in the control scheme were measured. The input voltage set to be 30V, with the switch frequency change from 40's to 100's, the output voltages change from 9.2V to 6V, the output current range is 18 mA to 30 mA. The efficiency ranges are 94% to 98%. The teaching target set for the ESN is the output voltage of the two-phase buck converter. The ESN will read data from two-phase buck converter's simulation, including input voltage, the frequency of the switches and based on that to compute the output voltage. / Master of Science / Buck converter is a power converter which drops high input voltage into a low output voltage in high efficiency. With this characteristic, it has been used in a great number of applications. Most of the buck converter optimized the maximum load to increase the efficiency, however, it will also increase the power consumption of the buck converter. For this reason, we propose a novel way of designing the two-phase buck converter optimize with Echo State Network(ESN). The inspiration of neural network is derived from the biological brain, similar with a human brain, the neural network also have self-learning ability. Reservoir computing is one kind of neural network, it can save more time on computing data and increase the efficiency at the same time. Compare with normal two-phase buck converter, the purposed two-phase buck converter optimize with ESN can increase the efficiency and also decrease the running time.

No description available.

Evolutions in microprocessor technology require the use of a high-frequency synchronous buck converter (SBC) in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency also causes more power loss on MOSFETs. Optimization of the MOSFETs plays an important role in the system performance. Circuit and device modeling is important in understanding the relationship between the device parameters and the power loss. The gate-to-drain charge (Qgd) is studied by a novel nonlinear model and compared with the simulation results. A new switching model is developed, which takes into account the effect of parasitic inductance on the switching process. Another model for dv/dt-induced false triggering-on relates the false-trigger-on voltage with the parasitic elements of the device and the circuits. Some techniques are proposed to reduce the simulation time of FEA in the circuit simulation. Based on this approach, extensive simulations are performed to study the switching performance of the MOSFET with the effect of the parasitic elements. Directed by the analytical models and the experience acquired in the circuit simulation, the MOSFET optimization is realized using FEA. Different optimization algorithms are compared. The experimental results show that the optimized MOSFETs surpass the mainstream commercialized products in both cost and performance. / Ph. D.