abstract: Synchronous buck converters have become the obvious choice of design for high efficiency voltage down-conversion applications and find wide scale usage in today's IC industry. The use of digital control in synchronous buck converters is becoming increasingly popular because of its associated advantages over traditional analog counterparts in terms of design flexibility, reduced use of off-chip components, and better programmability to enable advanced controls. They also demonstrate better immunity to noise, enhances tolerance to the process, voltage and temperature (PVT) variations, low chip area and as a result low cost. It enables processing in digital domain requiring a need of analog-digital interfacing circuit viz. Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC). A Digital to Pulse Width Modulator (DPWM) acts as time domain DAC required in the control loop to modulate the ON time of the Power-MOSFETs. The accuracy and efficiency of the DPWM creates the upper limit to the steady state voltage ripple of the DC - DC converter and efficiency in low load conditions. This thesis discusses the prevalent architectures for DPWM in switched mode DC - DC converters. The design of a Hybrid DPWM is presented. The DPWM is 9-bit accurate and is targeted for a Synchronous Buck Converter with a switching frequency of 1.0 MHz. The design supports low power mode(s) for the buck converter in the Pulse Frequency Modulation (PFM) mode as well as other fail-safe features. The design implementation is digital centric making it robust across PVT variations and portable to lower technology nodes. Key target of the design is to reduce design time. The design is tested across large Process (+/- 3σ), Voltage (1.8V +/- 10%) and Temperature (-55.0 °C to 125 °C) and is in the process of tape-out. / Dissertation/Thesis / M.S. Electrical Engineering 2013

Evolutions in microprocessor technology require the use of a high-frequency synchronous buck converter (SBC) in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency also causes more power loss on MOSFETs. Optimization of the MOSFETs plays an important role in the system performance. Circuit and device modeling is important in understanding the relationship between the device parameters and the power loss. The gate-to-drain charge (Qgd) is studied by a novel nonlinear model and compared with the simulation results. A new switching model is developed, which takes into account the effect of parasitic inductance on the switching process. Another model for dv/dt-induced false triggering-on relates the false-trigger-on voltage with the parasitic elements of the device and the circuits. Some techniques are proposed to reduce the simulation time of FEA in the circuit simulation. Based on this approach, extensive simulations are performed to study the switching performance of the MOSFET with the effect of the parasitic elements. Directed by the analytical models and the experience acquired in the circuit simulation, the MOSFET optimization is realized using FEA. Different optimization algorithms are compared. The experimental results show that the optimized MOSFETs surpass the mainstream commercialized products in both cost and performance. / Ph. D.

Buck converter is a power converter which drops high input voltage into a low output voltage in high efficiency. With this characteristic, it has been used in a great number of applications. Optimized the maximum load to increase the buck converter's efficiency at the cost of light load efficiency is a general way used in a traditional buck converter because it has a higher impact on power consumption. We propose a novel way of designing the two-phase buck converter with light load efficiency improvement in this thesis. The purposed two-phase buck converter uses RC delay to control switch frequency. Different frequency will affect the buck converter in output value and efficiency. RC delay includes two parts; part one connect with phase one, part two connect with phase two. After the test, when resister's value of part one is 100kΩ, and the capacitor's value is 50 pF, the resister's value of path two is 40kΩ, and the capacitors' value is 50 pF, the buck converter can reach maximum efficiency. The inspiration of the neural network is derived from the biological brain, neural is similar with the human neural, and the synaptic weights can treat as the connection between two nodes. Reservoir computing can be seen as an extension of the neural network since it is a framework for computation. Echo State Network(ESN) is one of the major types of reservoir computing, and it is a recurrent neural network. Compared with a neural network, it only trains output weights, which can save a lot of time but keep the accuracy of the training at the same time. The efficiency of the two-phase buck converter and power loss for each phase in the control scheme were measured. The input voltage set to be 30V, with the switch frequency change from 40's to 100's, the output voltages change from 9.2V to 6V, the output current range is 18 mA to 30 mA. The efficiency ranges are 94% to 98%. The teaching target set for the ESN is the output voltage of the two-phase buck converter. The ESN will read data from two-phase buck converter's simulation, including input voltage, the frequency of the switches and based on that to compute the output voltage. / Master of Science / Buck converter is a power converter which drops high input voltage into a low output voltage in high efficiency. With this characteristic, it has been used in a great number of applications. Most of the buck converter optimized the maximum load to increase the efficiency, however, it will also increase the power consumption of the buck converter. For this reason, we propose a novel way of designing the two-phase buck converter optimize with Echo State Network(ESN). The inspiration of neural network is derived from the biological brain, similar with a human brain, the neural network also have self-learning ability. Reservoir computing is one kind of neural network, it can save more time on computing data and increase the efficiency at the same time. Compare with normal two-phase buck converter, the purposed two-phase buck converter optimize with ESN can increase the efficiency and also decrease the running time.

In the thesis, a LED driver circuit that is applied in low power LED lighting with constant output current and Power Factor Correction (PFC) is presented. For power stage of LED driver, a non-insulated switching Buck power converter without transformer is used, and develop equivalent mathematical model and block diagram of Buck converter while its inductor current operating in Continuous Conduction Mode(CCM). Furthermore, the closed loop PFC control circuit is designed by time-domain and frequency-domain analysis. In addition, because of the classical PFC control configuration needs the expensive multiplier, a LED driver circuit with PFC without multiplier is presented in this thesis in order to reduce the system cost and space of the circuit. Then, we confirm the designed circuit by simulation and experiment. By the results, the proposed system achieves constant output current control and power factor can reach to 0.92.

A twin-buck converter with zero-voltage-transition (ZVT) is proposed in this thesis. The converter comprises two identical buck conversion units connected in parallel by an interleaved inductor. The ZVT is accomplished by the resonating the currents between the interleaved inductor and the parasitic capacitances of the power MOSFETs. The circuit efficiency can be further improved by introducing synchronous rectification to reduce the condition loss on the diodes. The detailed circuit analysis and operation characteristics are provided. A laboratory circuit rated at 300 W is designed and tested. Experimental results show that the switching losses can be effectively reduced by smoothly transiting the currents of the active power switches.

This thesis is to design an LED driver circuit with constant output current and Power Factor Correction(PFC) control. Switching power converter is applied for power stage of the LED driver circuit, a non-insulated Buck converter without transformer is used, and the inductor current of Buck converter is operating in Continuous Conduction Mode(CCM). According to the operating principle of Buck converter, the equivalent mathematical model and system block diagram is developed to establish the traditional closed loop PFC control circuit. The controller parameters are set up by time-domain and frequency-domain analysis to achieve the goal with constant output current and PFC control. Furthermore, the thesis presents a more effective PFC control method to reduce the cost of multiplier used in traditional PFC control method and overcome the congenital defect of Buck converter. Both two PFC control methods are confirmed and compared by simulation and experiment. The results show that the proposed control method has more effective performance and achieve constant output current for LED with high power factor by 0.966 under full-load condition.

DC/DC buck converters are cascaded in order to generate proper load voltages. Rectified line voltage is normally converted to 48V, which then, by a bus voltage regulating converter also called the line conditioner converter, is converted to the bus voltage, e.g. 12V. A polynomial controller converter transforms the 12V into to a suitable load voltage, a fraction of or some few voltages. All cascaded converters are individually controlled in order to keep the output voltage stable constant. In this presentation focusing on the polynomial controller converter implemented as Ericsson’s buck converter BMR450. In this paper modeling, discretization and control of a simple Buck converter is presented. For the given DC-DC-Converter-Ericsson BMR 450 series, analyzing the disturbance properties of a second order buck converter controllers by a polynomial controller. The project is performed in Matlab and Simulink. The controller properties are evaluated for measurement noise, EMC noise and for parameter changes. / +46-762795822

Hydrogen is a potential future energy storage medium to supplement a variety of renewable energy sources. It can be regarded as an environmentally-friendly fuel, especially when it is extracted from water using electricity obtained from solar panels or wind turbines. The focus in this thesis is on solar energy, and the theoretical background (i.e., PSCAD computer simulation) and experimental work related to a water-splitting, hydrogen-production system are presented. The hydrogen production system was powered by a photovoltaic (PV) array using a proton exchange membrane (PEM) electrolyser. The PV array and PEM electrolyser display an inherently non-linear current-voltage relationship that requires optimal matching of maximum operating power. Optimal matching between the PV system and the electrolyser is essential to maximise the transfer of electrical energy and the rate of hydrogen production. A DC/DC converter is used for power matching by shifting the PEM electrolyser I-V curve as closely as possible toward the maximum power the PV can deliver. By taking advantage of the I-V characteristics of the electrolyser (i.e., the DC/DC converter output voltage is essentially constant whereas the current increases dramatically), we demonstrated experimentally and in simulations that the hydrogen production of the PV-electrolyser system can be optimised by adjusting the duty cycle generated by the pulse-width modulation (PWM) circuit. The strategy used was to fix the duty cycle at the ratio of the PV maximum power voltage to the electrolyser operating voltage. A stand-alone PV energy system, using hydrogen as the storage medium, was designed. The system would be suitable for providing power for a family's house located in a remote area in the Libyan Sahara.

abstract: This work analyzes and develops a point-of-load (PoL) synchronous buck converter using enhancement-mode Gallium Nitride (e-GaN), with emphasis on optimizing reverse conduction loss by using a well-known technique of placing an anti-parallel Schottky diode across the synchronous power device. This work develops an improved analytical switching model for the GaN-based converter with the Schottky diode using piecewise linear approximations. To avoid a shoot-through between the power switches of the buck converter, a small dead-time is inserted between gate drive switching transitions. Despite optimum dead-time management for a power converter, optimum dead-times vary for different load conditions. These variations become considerably large for PoL applications, which demand high output current with low output voltages. At high switching frequencies, these variations translate into losses that contribute significantly to the total loss of the converter. To understand and quantify power loss in a hard-switching buck converter that uses a GaN power device in parallel with a Schottky diode, piecewise transitions are used to develop an analytical switching model that quantifies the contribution of reverse conduction loss of GaN during dead-time. The effects of parasitic elements on the dynamics of the switching converter are investigated during one switching cycle of the converter. A designed prototype of a buck converter is correlated to the predicted model to determine the accuracy of the model. This comparison is presented using simulations and measurements at 400 kHz and 2 MHz converter switching speeds for load (1A) condition and fixed dead-time values. Furthermore, performance of the buck converter with and without the Schottky diode is also measured and compared to demonstrate and quantify the enhanced performance when using an anti-parallel diode. The developed power converter achieves peak efficiencies of 91.7% and 93.86% for 2 MHz and 400 KHz switching frequencies, respectively, and drives load currents up to 6A for a voltage conversion from 12V input to 3.3V output. In addition, various industry Schottky diodes have been categorized based on their packaging and electrical characteristics and the developed analytical model provides analytical expressions relating the diode characteristics to power stage performance parameters. The performance of these diodes has been characterized for different buck converter voltage step-down ratios that are typically used in industry applications and different switching frequencies ranging from 400 KHz to 2 MHz. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2020

The future of microprocessors is unknown. Over the past 40 years, their historical trend has been for adopting smaller and more powerful designs that drive the world that we live in today. The state of the microprocessor business today faces a crossroad, wishing to continue on the historical trend of doubling the number of transistors on a chip every 18 months (Moore’s Law) but also facing the realistic task of needing to power these sophisticated devices. With the low voltages and high currents that are required for these microprocessors to operate, it poses a difficult task for the future designers of the voltage regulators that are used to power these microprocessors. The technique that has been widely adopted as the preferred method to power these devices is called a multiphase buck converter, or multiphase voltage regulator. This thesis is a continuation of and is aimed to improve previous work done by two former Cal Poly students, Kay Ohn and Ian Waters. A new design that uses an interleaving control scheme, careful component selection, an input LC filter, and a reduction in board size seeks to improve the efficiency, input current noise, and increase the current density of the original design. Research was first conducted to determine how to best make such improvements. The design phase ensued, which used design calculations and simulations to test if the proposed multiphase topology was plausible. Once the theory was fully proven, a real hardware circuit was created and tested to confirm the results. The results yield a multiphase design with improved input noise filtering, greater efficiency, more equal current sharing, and higher current density as compared to previous topologies in this field. Parameters such as output voltage ripple, load and line regulation, and transient response remained excellent, as they were with the previous work.