Les Alimentations Sans Interruption (ASI) ont pour rôle de protéger les charges sensibles. Leur utilisation nécessite l’usage de convertisseur de puissance AC/DC triphasé abaisseur et/ou élévateur de tension. Les ASI utilisent généralement une chaîne de conversion DC/DC+DC/AC ayant un rendement aux alentours de et sont souvent employées de façon continue. L’objectif de cette thèse est donc d’étudier un convertisseur DC/AC triphasé réversible en puissance susceptible de fonctionner en abaisseur et en élévateur de tension pour atteindre un rendement souhaité de 98% avec un minimum de 97,5%. L’étude s’oriente vers des architectures de convertisseurs peu conventionnelles, l’utilisation de semi-conducteurs grand gap (SiC) et de composants passifs à faible pertes. Une méthode de comparaison rapide qui est à la fois analytique et numérique est présentée pour dimensionner ces architectures en se basant sur les caractéristiques fournies par les constructeurs. La solution ‘Gradateur Onduleur Différentiel’ a été jugée comme la plus adaptée à nos besoins. Les choix techniques pour ce convertisseur sont détaillés, puis une étude de faisabilité présentée. Le convertisseur retenu est non linéaire et sa commande utilise des principes de fonctionnement atypiques, différentes stratégies de régulation sont donc présentées. Des tests sont effectués pour valider la commande mise en place et réaliser les essais fonctionnels et mesures de rendement. Enfin les résultats sont comparés aux prévisions et la solution proposée est finalement globalement comparée à la chaîne de conversion AC/DC+DC/DC classique. / Uninterruptible Power Supply (UPS) aim at quasi-instantaneous protection of critical loads. A DC to 3-phase AC stepup/stepdown converter is needed. For UPS, energy transfer using battery generally uses a 2-stage DC/DC+DC/AC conversion with an efficiency close to 96%. UPS are generally running permanently. The goal of this PhD is to optimize this conversion chain to aim at a target efficiency of 98% with a minimum requirement of 97%. To achieve this, our study will start with a survey of reversible architectures with both stepup and stepdown capability. Using wide bandgap semi-conductors and low-loss passive components are also part of this study. The power converter topologies are compared with a quick dimensioning method wich use both analytic analyse and simulation to realised an element selection based on characteristic given by the constructors. Eligible power converters are evaluated and compared and the “AC chopper+Inverter” architecture is found to best match our requirements. Then the technical choices of the power converter are detailed and a feasibility study is presented for the worst-case scenario. The selected power converter topology is non-linear and its control includes specific states, different strategies for the network and DC line electric parameter regulation are presented. To allow the verification of the proposed regulation, functional tests and efficiency measurement at different points are realised on the prototype. As a conclusion, the results gathered with the prototype are compared to those of a more conventional AC/DC+DC/DC power chain.

Made available in DSpace on 2014-06-11T19:22:35Z (GMT). No. of bitstreams: 0 Previous issue date: 2006-07-07Bitstream added on 2014-06-13T19:28:08Z : No. of bitstreams: 1 balestero_jpr_me_ilha.pdf: 1530452 bytes, checksum: 2f4b0b27a64698bd0dbc3bf2a5590ae7 (MD5) / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Este trabalho apresenta um novo conversor PWM CC-CC buck não isolado. O conversor é gerado a partir de uma célula de comutação de três estados, composta basicamente por dois interruptores ativos, dois passivos e dois indutores acoplados. Neste conversor apenas metade da potência da carga é processada pelos interruptores ativos, reduzindo assim a corrente de pico sobre estes à metade do valor da corrente de pico de saída, tornando-o importante para aplicações em potências mais elevadas. O volume dos elementos reativos (indutores e capacitores) é reduzido, pois, pela característica do conversor, a freqüência da ondulação da corrente e da tensão de saída é o dobro da freqüência de operação dos interruptores. Para uma menor freqüência de operação, diminuem-se as perdas na comutação. Devido à topologia do conversor, as perdas totais são distribuídas entre todos semicondutores, facilitando a dissipação de calor. Outra vantagem é possuir uma menor faixa de operação na região de descontinuidade em comparação com o conversor buck clássico, ou seja, a faixa de operação no modo de condução contínua é ampliada. É detalhada a abordagem através de análises qualitativa e quantitativa do emprego da célula de comutação de três estados no conversor buck, operando em toda faixa de variação da razão cíclica (0 .D .1). Além de toda a análise matemática e desenvolvimento através de simulação digital, um protótipo de 1kW foi implementado e testado em laboratório. Os principais resultados experimentais estão apresentados e discutidos neste trabalho. / This work presents a new PWM DC-to-DC non-isolated buck converter. The converter is generated using the three-state switching cell, comprised of two active switches, two diodes and two coupled inductors. In this converter only part of the load energy is processed by the active switches, reducing the peak current in these switches to half of the value to the peak of the load current. This feature permits to operate this topology in larger power levels. The volume of the power reactive elements (inductors and capacitors) is also decreased since the ripple frequency on the output is twice the switching frequency. For a lower operating frequency, the switching losses are decreased. Due to the topology of the converter, the total losses are distributed among all semiconductors, facilitating the dissipation of heat. Another advantage of this converter is the smaller region to operate in discontinuous conduction mode when compared to conventional buck converter or, in other words, the operation range in continuous conduction mode is enlarged. The theoretical approach is detailed through qualitative and quantitative analyses of the employment of the three states switching cell in the buck converter, operating in the entire every variation range of the duty cycle (0 < D < 1). Besides the mathematical analysis and development through digital simulation, a prototype of 1kW was implemented and tested at laboratory. The main experimental results are introduced and discussed in this work.

No description available.

Digital Switched mode power supplies are nowadays popular enough to be the obvious choice in many applications. Among all set-up and control techniques, the current mode DC-DC converter is often considered when performance and stability are of interest. This has also motivated all the “on chip” and ASIC implementations seen on the market, where current mode control technique is used. However, the development of FPGAs has created an important alternative to ASICs and DSPs. The flexibility and integration possibility is two important advantages among others. In this thesis report, an FPGA-based current mode buck/boost DC-DC converter is built in a stepwise manner, starting from the mathematical model. The goal is a simulation model which creates a basis for discussion about the advantages and disadvantages of current mode DC-DC converters, implemented in FPGAs.

A quantized control means that the control force is restricted to takes only a finite number of prescribed levels. The well-known bang-bang control or relay control belongs to this category. This kind of control has the advantage of simple circuit realization using electronic switches or relays that feature low power consumption in their on-off operation. However, quantized control introduces noise and distortion, and even worse its high nonlinearity makes the stabilizing compensator design difficult. This thesis applies the concept of dynamic sliding mode to the synthesis of a multi-level quantized control, with the aim to stabilize the system, perform reference tracking and attenuate the switching noise. The applicability of the presented sliding-mode quantized control is demonstrated on a three-level buck converter. Compared with the conventional PWM (Pulse-Width Modulation) scheme, it eliminates the use of a complex three-level PWM generator and a current sensor. A 12V/8V three-level buck converter with sliding mode quantized control is designed and realized, which shows the output voltage with 0.4625% of average DC error, 2.8988% of the static output ripple and 2.3% of load regulation error in response to the load current steps from 0A/3A to 3A/0A, at a slew rate of 6.25A/£gsec.

In the thesis, LED driver circuits which are applied in low power lighting LED with constant output current and Power Factor Correction are presented. The non-isolated Buck converter are used for the LED drivers. According to different operating mode of inductance current, Power Factor Correction are realized with both the method of Voltage Follower Approach Control under Discontinuous Conduction Mode and the method of Nonlinear Carrier Control under Continuous Conduction Mode. NLC doesn¡¦t need the multiplier which is used in traditional power factor correction, therefore NLC can reduce the system cost. The designed circuits are verified by simulation of IsSpice software and practical experiments. From simulation and experimental results, it shows the proposed approaches achieve the goal with high power factor and constant output current.

In this dissertation, we propose a circuit design and implementation of physical layer for FlexRay-based automotive communication systems which are expected to be widely used in car electronics for the years to come. To reduce the volume of electrical lines in a car and ensure safe connections, the automotive communication systems are more important than ever. FlexRay systems have been deemed as better than other existing solutions for the complicated in-vehicle networks. A low-voltage differential-signaling-like transmitter is proposed to drive the twisted pair of the FlexRay bus. Furthermore, a three-comparator scheme is used to carry out bit slicing and state recognition at the receiver end. A prototype system as well as a chip implemented by using a typical 0.18 £gm single-poly six-metal CMOS process is reported in this dissertation. Furthermore, an accurate clock signal is required in any control system, especially in the vehicle applications, where the ¡§safety¡¨ is the top priority. Because of the TDMA strategy (Time Division Multiple Access) was chosen for the FlexRay communication protocol, the system clock should not be drifting too much. A robust 20 MHz clock generator with process, supply voltage, and temperature compensation and a low-jitter 80 MHz phase-lock loop are proposed in this dissertation to reduce hostile environment effects. Finally, because the ¡§safety¡¨ and ¡§reliability¡¨ are top design requirements in the automobile electronics, we should also focus on the power supply design in the in-car communication networks. Therefore, a high tolerant and high efficiency voltage converter is proposed in this dissertation. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, this design is realized by a typical CMOS process without any thick-oxide device to tolerate input voltage range up to 3 times of the VDD voltage.

¡@¡@We consider output voltage regulation of a novel twin-buck switching power converters with so-called zero voltage switching (ZVS) and zero current switching (ZCS). In order to observe the constraints imposed by ZVS and ZCS, it is necessary to adopt the pulse frequency modulation (PFM) technique, which lead to a switching system with aperiodic operating cycles. The control design is based on a sampled data model of the original switching dynamics and a linear quadratic criterion that takes the at-sampling behaviour into account. The applicability of the proposed controller is validated via numerical simulations written in MATLAB and SIMULINK. The controller is realized using Field Programmable Gate Array (FPGA). The experimental results indicate that the feedback system have good transient response and adequate robustness margin against source and load variation, which verify the applicability of the proposed control design approach.

The portable electronics market is rapidly migrating towards more compact devices with multiple functionalities. Form factor, performance, cost and efficiency of these devices constitute the factors of merit of devices like cell phones, MP3 players and PDA's. With advancement in technology and more intelligent processors being used, there is a need for multiple high integrity voltage supplies for empowering the systems in portable electronic devices. Switched mode power supplies (SMPS's) are used to regulate the battery voltage. In an SMPS, maximum area is taken by the passive components such as the inductor and the capacitor. This work demonstrates a single inductor used in a buck converter with two output voltages from an input battery with voltage of value 3V. The main focus areas are low cross regulation between the outputs and supply of completely independent load current levels while maintaining desired values (1.2V,1.5V) within well controlled ripple levels. Dynamic hysteresis control is used for the single inductor dual output buck converter in this work. Results of schematic and post layout simulations performed in CADENCE prove the merits of this control method, such as nil cross regulation and excellent transient response.

Charge equalization is a major issue in the service of batteries since they are frequently connected in series to obtain higher output voltage levels for most applications. With series connection, imbalance may happen to the operating batteries during either charging or discharging periods. The imbalance among batteries concerns the operating efficiency and the battery lifetime. The main object of this dissertation is to solve the problem of charge inequality. The importance of charge equalization is first addressed. The problem is demonstrated by experiments of charging/discharging processes. Then, the techniques of battery charging and charge equalization are reviewed. To improve charge equalization, a dynamic balance charging scheme is developed on the basis of buck-boost conversion. The balance charging scheme can be realized by two configurations, that is, ¡§forward allotting¡¨ or ¡§backward allotting¡¨ configurations. The circuits are composed of several duplicated subcircuits and operated by digital control kernel, therefore, they are easy to be applied on battery sets with different numbers of batteries. By dynamically re-allocating the energy drawing from satiated batteries and allotted to hungry ones, the series-connected batteries can reach balance state more efficiently. The balance charging circuits can be employed during off-line or even discharging. However, on observing that the output voltage will vary in a big range when the battery set is discharged, the charge equalization can be integrated with voltage regulation on the output. Evolve from this idea, a balance discharging circuit¡@topology based on multi-winding transformer is proposed. The experiments in this dissertation are carried out on lead-acid batteries, therefore, the reactions and characteristics of lead-acid batteries are discussed. However, the proposed circuits are not restricted to be applied on lead-acid batteries only. Experimental results confirm the theoretical analyses and manifest the effectiveness of the designed circuits.