Coordinated Power Management in Heterogeneous Processors Indrani Paul 164 pages Directed by Dr. Sudhakar Yalamanchili With the end of Dennard scaling, the scaling of device feature size by itself no longer guarantees sustaining the performance improvement predicted by Moore’s Law. As industry moves to increasingly small feature sizes, performance scaling will become dominated by the physics of the computing environment and in particular by the transient behavior of interactions between power delivery, power management and thermal fields. Consequently, performance scaling must be improved by managing interactions between physical properties, which we refer to as processor physics, and system level performance metrics, thereby improving the overall efficiency of the system. The industry shift towards heterogeneous computing is in large part motivated by energy efficiency. While such tightly coupled systems benefit from reduced latency and improved performance, they also give rise to new management challenges due to phenomena such as physical asymmetry in thermal and power signatures between the diverse elements and functional asymmetry in performance. Power-performance tradeoffs in heterogeneous processors are determined by coupled behaviors between major components due to the i) on-die integration, ii) programming model and the iii) processor physics. Towards this end, this thesis demonstrates the needs for coordinated management of functional and physical resources of a heterogeneous system across all major compute and memory elements. It shows that the interactions among performance, power delivery and different types of coupling phenomena are not an artifact of an architecture instance, but is fundamental to the operation of many core and heterogeneous architectures. Managing such coupling effects is a central focus of this dissertation. This awareness has the potential to exert significant influence over the design of future power and performance management algorithms. The high-level contributions of this thesis are i) in-depth examination of characteristics and performance demands of emerging applications using hardware measurements and analysis from state-of-the-art heterogeneous processors and high-performance GPUs, ii) analysis of the effects of processor physics such as power and thermals on system level performance, iii) identification of a key set of run-time metrics that can be used to manage these effects, and iv) development and detailed evaluation of online coordinated power management techniques to optimize system level global metrics in heterogeneous CPU-GPU-memory processors.

We describe an adaptive, mid-level approach to the wireless device power management problem. Our approach is based on reinforcement learning, a machine learning framework for autonomous agents. We describe how our framework can be applied to the power management problem in both infrastructure and ad~hoc wireless networks. From this thesis we conclude that mid-level power management policies can outperform low-level policies and are more convenient to implement than high-level policies. We also conclude that power management policies need to adapt to the user and network, and that a mid-level power management framework based on reinforcement learning fulfills these requirements.

As VLSI technology scales, the enhanced performance of smaller transistors comes at the expense of increased power consumption. In addition to the dynamic power consumed by the circuits there is a tremendous increase in the leakage power consumption which is further exacerbated by the increasing operating temperatures. The total power consumption of modern processors is distributed between the processor core, memory and interconnects. In this research two novel power management techniques are presented targeting the functional units and the global interconnects. First, since most leakage control schemes for processor functional units are based on circuit level techniques, such schemes inherently lack information about the operational profile of higher-level components of the system. This is a barrier to the pivotal task of predicting standby time. Without this prediction, it is extremely difficult to assess the value of any leakage control scheme. Consequently, a methodology that can predict the standby time is highly beneficial in bridging the gap between the information available at the application level and the circuit implementations. In this work, a novel Dynamic Sleep Signal Generator (DSSG) is presented. It utilizes the usage traces extracted from cycle accurate simulations of benchmark programs to predict the long standby periods associated with the various functional units. The DSSG bases its decisions on the current and previous standby state of the functional units to accurately predict the length of the next standby period. The DSSG presents an alternative to Static Sleep Signal Generation (SSSG) based on static counters that trigger the generation of the sleep signal when the functional units idle for a prespecified number of cycles. The test results of the DSSG are obtained by the use of a modified RISC superscalar processor, implemented by SimpleScalar, the most widely accepted open source vehicle for architectural analysis. In addition, the results are further verified by a Simultaneous Multithreading simulator implemented by SMTSIM. Leakage saving results shows an increase of up to 146% in leakage savings using the DSSG versus the SSSG, with an accuracy of 60-80% for predicting long standby periods. Second, chip designers in their effort to achieve timing closure, have focused on achieving the lowest possible interconnect delay through buffer insertion and routing techniques. This approach, though, taxes the power budget of modern ICs, especially those intended for wireless applications. Also, in order to achieve more functionality, die sizes are constantly increasing. This trend is leading to an increase in the average global interconnect length which, in turn, requires more buffers to achieve timing closure. Unconstrained buffering is bound to adversely affect the overall chip performance, if the power consumption is added as a major performance metric. In fact, the number of global interconnect buffers is expected to reach hundreds of thousands to achieve an appropriate timing closure. To mitigate the impact of the power consumed by the interconnect buffers, a power-efficient multi-pin routing technique is proposed in this research. The problem is based on a graph representation of the routing possibilities, including buffer insertion and identifying the least power path between the interconnect source and set of sinks. The novel multi-pin routing technique is tested by applying it to the ISPD and IBM benchmarks to verify the accuracy, complexity, and solution quality. Results obtained indicate that an average power savings as high as 32% for the 130-nm technology is achieved with no impact on the maximum chip frequency.

As VLSI technology scales, the enhanced performance of smaller transistors comes at the expense of increased power consumption. In addition to the dynamic power consumed by the circuits there is a tremendous increase in the leakage power consumption which is further exacerbated by the increasing operating temperatures. The total power consumption of modern processors is distributed between the processor core, memory and interconnects. In this research two novel power management techniques are presented targeting the functional units and the global interconnects. First, since most leakage control schemes for processor functional units are based on circuit level techniques, such schemes inherently lack information about the operational profile of higher-level components of the system. This is a barrier to the pivotal task of predicting standby time. Without this prediction, it is extremely difficult to assess the value of any leakage control scheme. Consequently, a methodology that can predict the standby time is highly beneficial in bridging the gap between the information available at the application level and the circuit implementations. In this work, a novel Dynamic Sleep Signal Generator (DSSG) is presented. It utilizes the usage traces extracted from cycle accurate simulations of benchmark programs to predict the long standby periods associated with the various functional units. The DSSG bases its decisions on the current and previous standby state of the functional units to accurately predict the length of the next standby period. The DSSG presents an alternative to Static Sleep Signal Generation (SSSG) based on static counters that trigger the generation of the sleep signal when the functional units idle for a prespecified number of cycles. The test results of the DSSG are obtained by the use of a modified RISC superscalar processor, implemented by SimpleScalar, the most widely accepted open source vehicle for architectural analysis. In addition, the results are further verified by a Simultaneous Multithreading simulator implemented by SMTSIM. Leakage saving results shows an increase of up to 146% in leakage savings using the DSSG versus the SSSG, with an accuracy of 60-80% for predicting long standby periods. Second, chip designers in their effort to achieve timing closure, have focused on achieving the lowest possible interconnect delay through buffer insertion and routing techniques. This approach, though, taxes the power budget of modern ICs, especially those intended for wireless applications. Also, in order to achieve more functionality, die sizes are constantly increasing. This trend is leading to an increase in the average global interconnect length which, in turn, requires more buffers to achieve timing closure. Unconstrained buffering is bound to adversely affect the overall chip performance, if the power consumption is added as a major performance metric. In fact, the number of global interconnect buffers is expected to reach hundreds of thousands to achieve an appropriate timing closure. To mitigate the impact of the power consumed by the interconnect buffers, a power-efficient multi-pin routing technique is proposed in this research. The problem is based on a graph representation of the routing possibilities, including buffer insertion and identifying the least power path between the interconnect source and set of sinks. The novel multi-pin routing technique is tested by applying it to the ISPD and IBM benchmarks to verify the accuracy, complexity, and solution quality. Results obtained indicate that an average power savings as high as 32% for the 130-nm technology is achieved with no impact on the maximum chip frequency.

The 3D applications, until recently restricted to the desktops and workstations, are expanding into the mobile platforms, such as cellular phones and PDAs. Similar to the desktop, the consumers will expect high-quality 3D experience, and this is a big challenge. Handheld devices have slower processors that are less capable of computing large workloads, and the batteries have limited lifetimes, so for large and complex workload, we need an excellent power management policy for saving power. Besides, although mobile platforms have lower resolution than desktop, each pixel must still be rendered since the screen is closed to the observer¡¦s eye, or we will see some imperfections. For the reasons above, we make a point of performance optimization and power saving, and these rely on accuracy and fast workload estimation. We refer to some workload estimation methods which researchers have mentioned before, such as UW1, UW5, PID[8], Frame Structure[9], Signature Table[1], and hybrid power management policy[10].UW1 and UW5 both use the previous workload as the estimation workload. PID uses the feedback loop to correct the estimation workload. Frame Structure classifies frames into several structures, and sums the workload of each structure up as the estimation workload. Signature Table stores some 3D parameters in the table, and when a new frame comes in, the 3D parameters of this frame will compare with the table, if match, we use the workload in the table as the estimation workload. Our method is a hybrid policy of UW1 and UW5, and we will decide to use UW1 or UW5 when a new frame comes in. Finally we will compare the performance of each power management policy.

Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time \((<0.1V/\mu s)\). This global, slow DVFS cannot track the increasingly heterogeneous, fluctuating performance requirements of individual microprocessor cores and SoC components. Furthermore, traditional off-chip VRs add significant area overhead and component cost on the board. This thesis explores replacing a large portion of existing off-chip VRs with integrated voltage regulators (IVR) that can scale the voltage at a 50 mV/ns rate, which is 500 times faster than microsecond-scale voltage scaling with existing off-chip VRs. IVRs occupy 10 times smaller footprint than off-chip VRs, making it easy to duplicate them to provide per-core or per-IP-block voltage control. This thesis starts by summarizing the benefits of using IVRs to deliver power to SoCs. Based on a simulation study targeting a 1.6W, 4-core SoC, I show that greater than 20% energy savings is possible with fast, per-core DVFS enabled by IVRs. Next, I present two stand-alone IVR test-chips converting 1.8V and 2.4V to 0.4-1.4V while delivering maximum 1W to the output. Both test-chips incorporate a 3-level VR topology, which is suitable for integration because the topology allows for much smaller inductors (1nH) than existing inductor-based buck VRs. I also discuss reasons behind lower-than-simulated efficiencies in the test-chips and ways to improve. Finally, I conclude with future process technologies that can boost IVR conversion efficiencies and power densities. / Engineering and Applied Sciences

No description available.

Motivated by the goal of transition to a zero-carbon-emission-based economy for climate change mitigation, electrification opportunities are more promising in the transportation sector. Electric Vehicles (EVs) are at the forefront of the energy transition at an expanded rapid pace in the transportation sector. To enable and enhance the energy efficiency, advanced control and optimization will play an important role in EV systems and infrastructure. However, there are also some difficulties and limitations subject to the imperfection of management and control for EVs. Overall, to further the widespread adoption of EVs, the dissertation mainly includes two parts: 1) Power management for Plug-in Hybrid Electric Vehicles (PHEVs); 2) Charging control for Plug-in Electric Vehicles (PEVs). Chapter 2 deals with the power management and route planning problems for PHEVs, which aims to properly design the control algorithm to find the route that leads to the minimum energy consumption. Chapter 3 pays attention to the high workloads of the PEV in the electric power grids, which concentrates on studying a control algorithm leading to possible reductions in both computation and communication. Chapter 4 focuses on the charging control for PEVs, which explores how to improve the PEV charging efficiency while satisfying safety concerns. Chapter 5 modifies the results in Chapter 4 by taking battery capacity degradation into the optimization problem. This dissertation proceeds with Chapter 1 by reviewing the state-of-the-art control methods for PEVs and PHEVs. Chapter 2 studies a novel control scheme of route planning with power management for PHEVs. By considering the power management of PHEVs, we aim to find the route that leads to the minimum energy consumption. The scheme adopts a two-loop structure to achieve the control objective. Specifically, in the outer loop, the minimum energy consumption route is obtained by minimizing the difference between the value function of current round and the best value from all previous rounds. In the inner loop, the energy consumption index with respect to PHEV power management for each feasible route is trained with Reinforcement Learning (RL). Under the RL framework, a nonlinear approximator structure, which consists of an actor approximator and a critic approximator, is built to approximate control actions and energy consumption. In addition, the convergence of value function for PHEV power management in the inner loop and asymptotical stability of the closed-loop system are rigorously guaranteed. Chapter 3 investigates the self-triggered Model Predictive Control (MPC) with Integral Sliding Mode (ISM) method of a networked nonlinear continuous-time system subject to state and input constraints with additive disturbances and uncertainties. Compared with the standard MPC strategy, the proposed control scheme is designed for PEV charging to reduce the high communication loads caused by a large-scale population of vehicles under centralized charging control architecture. In the proposed scheme, the constrained optimization problem is solved aperiodically to generate control signals and the next execution time, leading to possible reductions in both computation and communication. The motivation of using ISM approach is to reject matched uncertainties. A self-triggered condition that involves a comparison between the cost function values with different execution periods is derived. Besides, the robust MPC with ISM control strategy is rigorously studied depending on the self-triggered scheme. Chapter 4 proposes a charging control algorithm for the valley-filling problem, while it meets individual charging requirements. We study a decentralized framework of PEV charging problem with a coordination task. An iterative learning-based model predictive charging control algorithm is developed to achieve the valley-filling performance. The design of the decentralized MPC meets individual charging requirements. The iterative learning method approximates the electricity price function and the system state sampled safe set to improve the accuracy of optimization problem calculations. The decentralized problem, in which the individual PEV minimizes its own charging cost, is formulated based on the sum of all power loads. Chapter 5 studies a modified charging control algorithm based on the previous charging control algorithm in Chapter 4. We propose a charging control algorithm for PEVs using a decentralized MPC framework supplemented by the iterative learning method. By considering the battery aging of PEVs, we aim to find the optimal charging rate that leads to valley-filling performance. The scheme adopts the iterative learning-based method to solve the optimal control problem with the battery aging model. Specifically, the sampled safe set and price function are updated accordingly as the iteration number increases. The battery aging model involves the cost function to approach the real charging scenario. In addition, the recursive feasibility of the proposed optimal control problem for PEV charging with battery aging and asymptotical stability of the closed-loop system are rigorously studied. Finally, in Chapter 6, the conclusions of the dissertation and some avenues for future potential research are presented. / Graduate / 2023-04-07

It is perceived that Moore's Law will prevail at least for the next decade with the continuous advancement of processing technologies for integrated circuits. According to Intel's roadmap, over one billion transistors will be integrated in one processor by the year 2010; the processor's clock speed will approach 15 GHz; the core static currents will increase up to 200 A; the dynamic current slew rate will rise up to 250 A/ns; and the core voltage will decrease to 0.8 V. The rapid advancement of processor technology has posed stringent challenges to power management for both an efficient power delivery and an accurate voltage regulation. The primary objectives of this dissertation are to understand the fundamental limitations of the state-of-the-art solution for the power management, and hence to support possible solutions for meeting the power requirement of the next generations of processors. First, today's voltage-regulator module (VRM) design, which is based on the multiphase interleaving buck topology, is thoroughly analyzed. The analysis results of the control bandwidths versus the VRM transient voltage spikes highlight the trend of high-frequency VRM design for smaller size and faster transient response. Based on the concept of achieving constant VRM output impedance, design guidelines are proposed for different kinds of control methods. However, the high switching-related losses in the conventional multiphase buck converter limit its further applications. This dissertation proposes a series of new topologies in order to break through the barriers by applying an inductor-coupling or autotransformer structure to reduce the switching-related losses by extending the duty cycle. Then, this dissertation pushes the topology innovation further by introducing soft-switching quasi-resonant converters for the VRM design. The combination of the quasi-resonant and active-clamped concepts derives a family of new converters, which can eliminate all the switching and body-diode losses. The experimental results at 1-2MHz switching frequencies prove that the proposed solutions for the VRM design can realize very high efficiency and high power density. / Ph. D.

The power consumption of smart camera in car black box varies significantly between light load and heavy load. The high efficiency voltage regulator is necessary in prolong the life of smart camera battery. Since the smart camera only recording the video when car is driving, the most time of the smart camera works in the sleep mode. Hence the light load efficiency is important in this application, however, conventional buck converter usually have high efficiency at heavy load but poor efficiency at light load. To increase the light load efficiency of buck converter, this research continues Yeago's two phase buck converter with optimum phase selection control and Zhao's two mode buck converter to further improve the light load efficiency for the target application. With 5V input voltage and 1.2V output voltage, the proposed two-mode synchronous buck converter can supply the load power from 12mW to 1.44W. To improve the light load efficiency of conventional buck converter, the proposed design applied Wei's baby buck concept to provide another light load power stage to reduce the switching loss and driving loss at light load. Then, the variable frequency ripple-based constant on-time control with discontinuous conduction mode (DCM) in light load is applied to the baby-buck mode to reduce the switching frequency to further reduce the switching loss. Also, the baby-buck mode uses the synchronous buck topology to remove the diode in asynchronous converter to increase the efficiency at light load. Finally, a sensorless mode selector remove the sensing resistor in power stage to increase the efficiency for entire load range, especially for the heavy load. The mode selector can select the optimum mode for different load condition, and the opposite mode would completely shut down to save the loss. The proposed design is implement in CMOS 0.25um technology. The proposed monolithic buck converter which include the power stage of heavy buck mode, baby-buck mode and the controller is fabricated. The measurement result shows the close loop efficiency varies from 70%-83% toward the entire load range. / Master of Science