This project is intended to findsuitable circuit architecture forefficient power transmission where thepower supply is low.Two circuits will be built. The firstwill receive high AC which correspondsto the voltage created in a piezoelement once subjected to stress fromfoot steps It will deliver 3.3DC.The second circuit will receive low ACwhich will represent voltage receivedfrom a wireless transfer.Due to a failing high voltage powersupply the second circuit was never putto practice. The idea was to send a wavefile through an OP-amplifier to simulatethe voltage from the piezo element. Thevoltage was then rectified and convertedto 3.3DC.Circuit 2 was tested with a frequencygenerator as power supply. The voltagewas transformed, rectified and at lastconverted to 3.3DC through a voltageregulator. Due to lack of deliveredpower from the frequency generator itwas necessary to duty cycle the load tolimit the power dissipation.The power dissipation in the voltageregulator was limited as well byswitching it on and off. When switchedoff a capacitor was charged. When in onmode the capacitor was emptied into thevoltage regulator. / Det här projektet är ämnat att hittalämpliga kretsarkitetkturer för braeffektöverföring där energikällorna ärmycket begränsade.Två kretsar ska byggas. Den första skata emot hög växelspänning motsvarandespänningen som uppkommer i ettpiezoelement vilket utsätts för växlandetryck. I det här fallet trycket från enmänniskas fotsteg. Kretsen ska leverera3.3V likspänning.Den andra kretsen ska ta emot en lågväxelspänning, vilken motsvarar spänningfrån en trådlös överföring, och leverera3.3V.Krets 1 blev aldrig testad på grund avett fallerande högspänningsaggregat.Genom att skicka en wav-fil genom en OPförstärkareskulle en simulerad spänningfrån piezoelementet användas. Därefterskulle spänningen likriktas ochkonverteras ner till 3.3V.Krets 2 testades med en signalgeneratorsom spänningskälla. Spänningentransformerades först upp innan denlikriktades och skickades in i enspänningsreglator för att därefter ge ut3.3V. Med en liten levererad effekt frånsignalgeneratorn var det nödvändigt attbegränsa effektåtgången i lasten genompulsbreddmodulering. Effektåtgången ispänningsreglatorn begränsades ocksågenom att stänga av och på IC:n(spänningsregulatorn). När IC:n varavstängd laddades en kondensator upp somsedan tömdes i IC:n då den aktiveradesigen.

This dissertation describes the development of voltage regulators for the purpose of power reduction and further scaling in highly integrated system-on-chip products. Emphasis is placed on the architecture and implementation of integrated voltage regulation using commercially available components, standard CMOS technology, and a practical controller. The research spans the fundamental elements, architectural aspects, and detailed analog integrated circuit design. / text

Multi-phase Buck is widely used in Voltage Regulator Modules design because of its low cost and simplicity. But this topology also has a lot of drawbacks. One of the most fundamental drawback is that it has narrow duty cycles when it operates at high switching frequency with low output voltage (for example 1V). Narrow duty cycles yield high switching loss which limits the switching frequency of Buck; making it difficult to design a Buck based VRM that can achieve high efficiency at a high switching frequency. In this thesis three new non-isolated full bridge topologies will be introduced to solve the aforementioned problems of Buck. One is a new non-isolated full bridge topology, this new topology use a transformer to extend the duty cycle and it capable to achieve zero voltage switching. Experimental results demonstrate that it has significant advantages over multi-phase Buck. In some applications when huge output current is required, several converters are paralleled to supply the current that is not an optimal solution. Two two-phase non-isolated full bridge topologies are proposed to solve this problem. They double the output power of one-phase non-isolated full bridge, and achieve higher efficiency with fewer switches compared with parallel two non-isolated full bridge converters. Non-isolated VRM usually is used for personal computers, VRM for servers is called power pod, and usually isolation is required for power pod due to safety considerations. Server usually require much more power than personal computers, their power consumption is around several KW. To provide the power for the server a few power modules will need to be paralleled, this kind solution is expensive and make current sharing complex. In this thesis two new two-phase isolated full bridge topologies are proposed. They are capable to operate at soft switching mode. And they double the output power compared with conventional full bridge converter. Compared with parallel two full bridge converters, they can achieve higher efficiency with fewer switches. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-02-28 09:53:50.23

Traditional methods of system-on-chip (SoC) power management based on dynamic voltage and frequency scaling (DVFS) is limited by 1) cores/IP blocks sharing a voltage domain provided by off-chip voltage regulators (VR) and 2) slow voltage scaling time \((<0.1V/\mu s)\). This global, slow DVFS cannot track the increasingly heterogeneous, fluctuating performance requirements of individual microprocessor cores and SoC components. Furthermore, traditional off-chip VRs add significant area overhead and component cost on the board. This thesis explores replacing a large portion of existing off-chip VRs with integrated voltage regulators (IVR) that can scale the voltage at a 50 mV/ns rate, which is 500 times faster than microsecond-scale voltage scaling with existing off-chip VRs. IVRs occupy 10 times smaller footprint than off-chip VRs, making it easy to duplicate them to provide per-core or per-IP-block voltage control. This thesis starts by summarizing the benefits of using IVRs to deliver power to SoCs. Based on a simulation study targeting a 1.6W, 4-core SoC, I show that greater than 20% energy savings is possible with fast, per-core DVFS enabled by IVRs. Next, I present two stand-alone IVR test-chips converting 1.8V and 2.4V to 0.4-1.4V while delivering maximum 1W to the output. Both test-chips incorporate a 3-level VR topology, which is suitable for integration because the topology allows for much smaller inductors (1nH) than existing inductor-based buck VRs. I also discuss reasons behind lower-than-simulated efficiencies in the test-chips and ways to improve. Finally, I conclude with future process technologies that can boost IVR conversion efficiencies and power densities. / Engineering and Applied Sciences

Increasing power consumption and heat dissipation are becoming urgent challenges for processors today and in the future. Digital power control architectures in which processors closely interact with voltage regulators are becoming necessary to enhance system energy efficiency. Digital techniques offer advantages such as flexibility, fewer external components and reduced overall cost as compared to conventional analog techniques. The primary objective of this thesis is to develop new digital control architecture for processor voltage regulators with low complexity and high dynamic performance. A digital control technique to naturally implement the desired output impedance is proposed. In this technique, Adaptive Voltage Positioning (AVP) is implemented by generating a dynamic voltage reference and a dynamic current reference to achieve the desired output impedance. A dual-voltage-loop control with dynamic reference step adjustment, non-linear control and a dedicated transient detection circuit is proposed to improve the dynamic performance. The dynamic reference step adjustment method lowers the high speed requirement of reference update clock; the non-linear control minimizes the transient-assertion-to-action delay and maximizes the inductor current slew rate; and the transient detection circuit recognizes the load transient state in a manner adaptive to the amount and slew rate of load transient. Theoretical, simulation and experimental results prove the effective operation and excellent performance of the controller. Finally, the dynamic performance of the voltage regulator with the proposed digital controller under large-step load oscillations is proven by simulation and experimental results. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-07-31 13:14:52.149

Low dropout regulators (LDOs) are important components for power management in modern integrated circuits. With the continued scaling down of power supply voltage, digital LDOs have become a more attractive design choice since they avoid the difficulty of designing high-gain amplifiers with low voltage. This thesis investigates techniques for both modeling and enhancement of digital LDO transient response. It discusses the importance of the resistance in the output stage of an LDO, and proposes a simulation model for examining LDO transient response. In addition, the thesis studies circuit techniques to improve LDO transient response. Different LDO circuits are implemented and compared in this study.

Advances in very large scale integration (VLSI) technologies impose challenges for voltage regulator modules (VRM) to deliver high-quality power to modern microprocessors. As an enabling technology, multiphase converters have become the standard practice in VRM industry. The primary objectives of this dissertation are to develop advanced topologies and innovative integrated magnetics for high-efficiency, high-power-density and fast-transient VRMs. The optimization of multiphase VRMs has also been addressed. Today's multiphase VRMs are almost universally based on the buck topology. With increased input voltage and decreased output voltage, the multiphase buck converter suffers from a very small duty cycle and cannot achieve a desirable efficiency. The multiphase tapped-inductor buck converter is one of the simplest topologies with a decent duty cycle. However, the leakage inductance of its tapped inductors causes a severe voltage spike problem. An improved topology, named the multiphase coupled-buck converter, is proposed. This innovative topology enables the use of a larger duty cycle with clamped device voltage and recovered leakage energy. Under the same transient responses, the multiphase coupled-buck converter has a significantly better efficiency than the multiphase buck converter. By integrating all the magnetic components into a single core, in which the windings are wound around the center leg and the air gaps are placed on the two outer legs, it is possible for multiphase VRMs to further improve efficiency and cut the size and cost. Unfortunately, this structure suffers from an undesirable core structure and huge leakage inductance. An improved integrated magnetic structure is proposed to overcome these limitations. All the windings are wound around the two outer legs and the air gap is placed on the center leg. The improved structure also features the flux ripple cancellation in the center leg and strongly reverse-coupled inductors. Both core loss and winding loss are reduced. The steady-state current ripples can be reduced without compromising the transient responses. The overall efficiency of the converter is improved. The input inductor can also be integrated in the improved integrated magnetic structure. Currently, selecting the appropriate number of channels for multiphase VRMs is still an empirical trial-and-error process. This dissertation proposes a methodology for determining the right number of channels for the optimal multiphase design. The problem formulation and general method for the optimization are proposed. Two examples are performed step by step to demonstrate the proposed optimization methodology. Both are focused on typical VRM 9.0 designs for the latest Pentium 4® microprocessors and their results are compared with the industry practice. / Ph. D.

No description available.

Microprocessors in today's computers continue to get faster and more powerful. From the Intel 80X86 series to today's Pentium IV, CPUs have greatly improved in performance. Accordingly, their power consumption has increased dramatically [1][2]. An evolution began in power loss reduction when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. In order to provide the power as quickly as possible, the voltage regulator (VR), a dedicated DC-DC converter, is placed in close proximity to power the processor. At first, VRs drew power from the 5V output of the silver box. As the power delivered through the VR increased so dramatically, it became no longer efficient to use the 5V bus. Then for desktop and workstation applications, the VR input voltage moved to the 12V output of the silver box. For laptop application, the VR input voltage range covers the battery voltage range and the adaptor voltage. In the meantime, microprocessors will run at very low voltage (sub 1V), and will consume up to 150A of current, and will have dynamics of about 400A/us. The current VR solution is the 12V-input multiphase interleaved buck converter. The switching frequency is around 300KHz. This approach has several limitations for the future. OSCON capacitor is one limitation due to its large ESR and ESL; the low switching frequency the second limitation and the large inductance is the third limitation. Analysis shows that the all-ceramic solution is a better solution than the OSCON solution when the VR switching frequency reaches 1MHz. However, the 12V-input multiphase buck converter suffers low efficiency at high switching frequency, which rules out a legitimate chance of the current VR topology benefiting from high switching frequency. The extreme duty cycle is the fundamental reason why the 12V-input multiphase buck converter is not suitable for future VRs. Employing the transformer concept can extend duty cycle, and therefore offer an opportunity to improve efficiency. The push-pull buck (PPB) converter is proposed as a solution. The efficiency is improved compared with the buck converter. Integrated magnetic techniques can be used to further improve the efficiency and simplify the implementation. The impact of transformer concept on transient response is analyzed. The PPB converter efficiency is still not satisfactory at 1MHz due to the switching loss. Switching loss being a barrier, soft switching is needed. The proposed soft-switched phase-shift buck (PSB) converter achieves soft switching for the top switches. Highly efficient power conversion is achieved at high switching frequency. The integrated magnetics makes the implementation concise and delivers good performance. Given that the PSB converter has good performance, the matrix-transformer phase-shift buck (MTPSB) converter is a simplified version of the four-phase PSB converter. The MTPSB converter trades off some performance with circuit complexity. This feature establishes itself as a very cost-effective solution for future VRs. The magnetic structure of the MTPSB converter is also very simple with the use of integrated magnetics. Mobile CPUs are used in laptop computers. They require very challenging power management. The challenges for a laptop VR are different from and greater than those for a desktop VR. A laptop VR needs to have high efficiency at both heavy load and light load, good transient response and small and light form-factor, and work well with the wide input voltage range. Future mobile CPUs demand very aggressive power. The current single-stage VR approach cannot provide a suitable solution for the future. The PSB converter has disadvantages in light-load efficiency and does not work well with wide input voltage range; therefore it is not a suitable solution for laptop VRs although it is still a suitable solution for desktop VRs. The two-stage approach solves the wide-input-voltage-range issue and improves efficiency at heavy load significantly. The intermediate bus voltage Vbus is a very important parameter impacting overall efficiency. There is not one optimal Vbus value for all load conditions. The heavier the load, the higher the optimal Vbus. Based on this fact, the ABVP control is proposed. Vbus is adaptively positioned according to the load current therefore optimal Vbus is achieved under most conditions. Experimental results verify the theoretical prediction. The ONP control is another control scheme proposed to improve the light-load efficiency. By selecting optimal number of phases based on mobile processor power states, the VR light-load efficiency is improved. Experimental results show the proof. The baby-buck concept is the third concept proposed to improve the very-light-load efficiency. By operating the baby-buck channel, the two-stage VR improves efficiency at very light load. The two-stage VR featuring the three proposed control schemes has much higher efficiency than the single-stage VR over a very wide load range; therefore the battery life is extended. The two-stage VR with the proposed control schemes is a good solution for future laptop VRs. The problem solving process in this work proves that good solutions in isolated converters can be modified to fit into the non-isolated application. Non-isolated converters and isolated converters are not two separated worlds. On the contrary, these two worlds have many things in common. Good concepts can be transplanted from one world to another with minor modification and many problems can be solved this way. Another proven point in this work is that sometimes the solution is a fundamental, such as the change of power delivery architecture. One should not be limited by what is available right now, and should think outside the box. Once a fundamental change is made, it is very beneficial to take full advantage of the change, as it provides new opportunities. / Ph. D.

It is perceived that Moore's Law will prevail at least for the next decade with the continuous advancement of processing technologies for integrated circuits. According to Intel's roadmap, over one billion transistors will be integrated in one processor by the year 2010; the processor's clock speed will approach 15 GHz; the core static currents will increase up to 200 A; the dynamic current slew rate will rise up to 250 A/ns; and the core voltage will decrease to 0.8 V. The rapid advancement of processor technology has posed stringent challenges to power management for both an efficient power delivery and an accurate voltage regulation. The primary objectives of this dissertation are to understand the fundamental limitations of the state-of-the-art solution for the power management, and hence to support possible solutions for meeting the power requirement of the next generations of processors. First, today's voltage-regulator module (VRM) design, which is based on the multiphase interleaving buck topology, is thoroughly analyzed. The analysis results of the control bandwidths versus the VRM transient voltage spikes highlight the trend of high-frequency VRM design for smaller size and faster transient response. Based on the concept of achieving constant VRM output impedance, design guidelines are proposed for different kinds of control methods. However, the high switching-related losses in the conventional multiphase buck converter limit its further applications. This dissertation proposes a series of new topologies in order to break through the barriers by applying an inductor-coupling or autotransformer structure to reduce the switching-related losses by extending the duty cycle. Then, this dissertation pushes the topology innovation further by introducing soft-switching quasi-resonant converters for the VRM design. The combination of the quasi-resonant and active-clamped concepts derives a family of new converters, which can eliminate all the switching and body-diode losses. The experimental results at 1-2MHz switching frequencies prove that the proposed solutions for the VRM design can realize very high efficiency and high power density. / Ph. D.