This thesis includes two research topics. The first topic is a linear LDO regulator. The second one is a low noise amplifier (LNA). Both of the circuits can be applied to a totally implantable micro-electrical neural interfacing SOC. The linear LDO regulator is enhanced with a novel compensation technology, called modified NMCF (nested Miller compensation with feedforward Gm stage), resulting in that its performance is independent of the off-chip capacitor and its ESR (equivalent series resistor). The proposed compensation method ensures the stability of the feedback loop and the large enough phase margin of the LDO (low dropout) regulator. The power supply rejection ratio is 30 dB (operating at [200 Hz, 3 MHz] and a load of [50

As portable electronics constantly find their way into the hands of eager consumers, the demands placed on these products and their circuits are ever increasing. More features and more performance are continuously demanded by consumers. This feature-driven market has brought with it several constraints on the type of circuits utilized in developing these portable devices. Cell-Phones, PDA's, MP3 players and various other portable electronics require different voltage levels to power different architectures that realize the many features within the device. This work demonstrates a technique to design Programmable Low Power Low Dropout Voltage Regulators (LDO). The LDO proposed in this research utilizes a fast-transient feedback loop in order to improve transient response and guarantee stability in all the programmable output levels. Specifically, the main parameters to be improved are stability over the entire load current range, reduced overshoot and undershoot variations in transient response, reduction of LDO deflection voltage, minimization of standby current and low voltage (Vin = 1.2V) operation.

abstract: The constant scaling of supply voltages in state-of-the-art CMOS processes has led to severe limitations for many analog circuit applications. Some CMOS processes have addressed this issue by adding high voltage MOSFETs to their process. Although it can be a completely viable solution, it usually requires a changing of the process flow or adding additional steps, which in turn, leads to an increase in fabrication costs. Si-MESFETs (silicon-metal-semiconductor-field-effect-transistors) from Arizona State University (ASU) on the other hand, have an inherent high voltage capability and can be added to any silicon-on-insulator (SOI) or silicon-on-sapphire (SOS) CMOS process free of cost. This has been proved at five different commercial foundries on technologies ranging from 0.5 to 0.15 μm. Another critical issue facing CMOS processes on insulated substrates is the scaling of the thin silicon channel. Consequently, the future direction of SOI/SOS CMOS transistors may trend away from partially depleted (PD) transistors and towards fully depleted (FD) devices. FD-CMOS are already being implemented in multiple applications due to their very low power capability. Since the FD-CMOS market only figures to grow, it is appropriate that MESFETs also be developed for these processes. The beginning of this thesis will focus on the device aspects of both PD and FD-MESFETs including their layout structure, DC and RF characteristics, and breakdown voltage. The second half will then shift the focus towards implementing both types of MESFETs in an analog circuit application. Aside from their high breakdown ability, MESFETs also feature depletion mode operation, easy to adjust but well controlled threshold voltages, and fT's up to 45 GHz. Those unique characteristics can allow certain designs that were previously difficult to implement or prohibitively expensive using conventional technologies to now be achieved. One such application which benefits is low dropout regulators (LDO). By utilizing an n-channel MESFET as the pass transistor, a LDO featuring very low dropout voltage, fast transient response, and stable operation can be achieved without an external capacitance. With the focus of this thesis being MESFET based LDOs, the device discussion will be mostly tailored towards optimally designing MESFETs for this particular application. / Dissertation/Thesis / Ph.D. Electrical Engineering 2010

abstract: Power management plays a very important role in the current electronics industry. Battery powered and handheld applications require novel power management techniques to extend the battery life. Most systems have multiple voltage regulators to provide power sources to the different circuit blocks and/or sub-systems. Some of these voltage regulators are low dropout regulators (LDOs) which typically require output capacitors in the range of 1's to 10's of µF. The necessity of output capacitors occupies valuable board space and can add additional integrated circuit (IC) pin count. A high IC pin count can restrict LDOs for system-on-chip (SoC) solutions. The presented research gives the user an option with regard to the external capacitor; the output capacitor can range from 0 - 1µF for a stable response. In general, the larger the output capacitor, the better the transient response. Because the output capacitor requirement is such a wide range, the LDO presented here is ideal for any application, whether it be for a SoC solution or stand-alone LDO that desires a filtering capacitor for optimal transient performance. The LDO architecture and compensation scheme provide a stable output response from 1mA to 200mA with output capacitors in the range of 0 - 1µF. A 2.5V, 200mA any-cap LDO was fabricated in a proprietary 1.5µm BiCMOS process, consuming 200µA of ground pin current (at 1mA load) with a dropout voltage of 250mV. Experimental results show that the proposed any-cap LDO exceeds transient performance and output capacitor requirements compared to previously published work. The architecture also has excellent line and load regulation and less sensitive to process variation. Therefore, the presented any-cap LDO is ideal for any application with a maximum supply rail of 5V. / Dissertation/Thesis / M.S. Electrical Engineering 2012

The thesis is composed of two topics: a power-saving DRAMs with an adaptive refreshing clock generator, and a high precision low dropout regulator with nested feedback loops. In the first topic, an adaptive refreshing circuitry design for DRAMs is presented in this work. The proposed refreshing circuitry utilizes a voltage comparator to monitor the voltage drop caused by the data loss of a memory cell resulted from leakage currents to dynamically adjust the refreshing period of DRAM cells. A process variation monitor is also included in the proposed design to compensate the process drifting problem. Therefore, the proposed design is insensitive to temperature variations as well as process drifts. The period of the refreshing clock is automatically adjusted to save a great portion of standby power of DRAMs. A 4-Kb DRAM is implemented using a typical 0.13-£gm 1P8M digital CMOS process. Post-layout simulation results and a prototype on silicon justify the correctness of the adaptive refreshing cycles generated by the proposed design. In the second topic, a high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an Error Amplifier, the independence of off-chip capacitor and ESR is ensured for different load currents and operating voltages. Therefore, in low Iddq or low voltage scenarios, the total error of the output voltage caused by line and load variations is less than ¡Ó3% according to the on-silicon measurement results.

The thesis is composed of two topics : a charger circuit of Li-ion batteries for wireless biomedical systems and a capacitor-less low dropout regulator¡]LDO¡^. The first topic discloses a charger circuit of Li-ion batteries using 2P4M 0.35-£gm CMOS process, which comprises a small bias circuit, a comparator with hysteresis, a transistor voltage divider circuit, a power MOS, and a Li-ion charger with a cut-off voltage and a recharge voltage. The proposed design receives a 13.56 MHz carrier with 5¡Ó0.2 V amplitude to charge the Li-ion batteries with a small constant current. The second topic reveals a low dropout regulator ¡]LDO¡^ without capacitor load and ESR, including a bias circuit, an error amplifier, and a Flipped Voltage Follower circuit generating a stable output voltage independent on different loads. The proposed design improves the input voltage limitation of Flipped Voltage Follower by compensating phase margin such that the proposed design shows a good transient response and stability without any output capacitor. The proposed LDO is implemented by 1P6M 0.18-um CMOS process, which can operate correctly given an input voltage range from 3.3~4.2 V.

Low dropout regulators (LDOs) are important components for power management in modern integrated circuits. With the continued scaling down of power supply voltage, digital LDOs have become a more attractive design choice since they avoid the difficulty of designing high-gain amplifiers with low voltage. This thesis investigates techniques for both modeling and enhancement of digital LDO transient response. It discusses the importance of the resistance in the output stage of an LDO, and proposes a simulation model for examining LDO transient response. In addition, the thesis studies circuit techniques to improve LDO transient response. Different LDO circuits are implemented and compared in this study.

abstract: State of art modern System-On-Chip architectures often require very low noise supplies without overhead on high efficiencies. Low noise supplies are especially important in noise sensitive analog blocks such as high precision Analog-to-Digital Converters, Phase Locked Loops etc., and analog signal processing blocks. Switching regulators, while providing high efficiency power conversion suffer from inherent ripple on their output. A typical solution for high efficiency low noise supply is to cascade switching regulators with Low Dropout linear regulators (LDO) which generate inherently quiet supplies. The switching frequencies of switching regulators keep scaling to higher values in order to reduce the sizes of the passive inductor and capacitors at the output of switching regulators. This poses a challenge for existing solutions of switching regulators followed by LDO since the Power Supply Rejection (PSR) of LDOs are band-limited. In order to achieve high PSR over a wideband, the penalty would be to increase the quiescent power consumed to increase the bandwidth of the LDO and increase in solution area of the LDO. Hence, an alternative to the existing approach is required which improves the ripple cancellation at the output of switching regulator while overcoming the deficiencies of the LDO. This research focuses on developing an innovative technique to cancel the ripple at the output of switching regulator which is scalable across a wide range of switching frequencies. The proposed technique consists of a primary ripple canceller and an auxiliary ripple canceller, both of which facilitate in the generation of a quiet supply and help to attenuate the ripple at the output of buck converter by over 22dB. These techniques can be applied to any DC-DC converter and are scalable across frequency, load current, output voltage as compared to LDO without significant overhead on efficiency or area. The proposed technique also presents a fully integrated solution without the need of additional off-chip components which, considering the push for full-integration of Power Management Integrated Circuits, is a big advantage over using LDOs. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

No description available.

Low drop out (LDO) voltage regulators are widely used for post regulating the switching ripples generated by the switched mode power supplies (SMPS). Due to demand for portable applications, industry is pushing for complete system on chip power management solutions. Hence, the switching frequencies of the SMPS are increasing to allow higher level of integration. Therefore, the subsequent post-regulator LDO must have good power supply rejection (PSR) up to switching frequencies of SMPS. Unfortunately, the conventional LDOs have poor PSR at high frequencies. The objective of this research is to develop novel LDO regulators that can achieve good high frequency PSR performance. In this thesis, two PSR improvement methods are presented. The first method proposes a novel power supply noise-cancelling scheme to improve the PSR of an external-capacitor LDO. The proposed power supply noise-cancelling scheme is designed using adaptive power consumption, thereby not degrading the power efficiency of the LDO. The second method proposes a feed forward ripple cancellation technique to improve the PSR of capacitor-less LDO; also a dynamically powered transient improvement scheme has been proposed. The feed forward ripple cancellation is designed by reusing the load transient improvement block, thus achieving the improvement in PSR with no additional power consumption. Both the projects have been designed in TSMC 0.18 μm technology. The first method achieves a PSR of 66 dB up to 1 MHz where as the second method achieves a 55 dB PSR up to 1 MHz.