The thesis is composed of two topics: a power-saving DRAMs with an adaptive refreshing clock generator, and a high precision low dropout regulator with nested feedback loops. In the first topic, an adaptive refreshing circuitry design for DRAMs is presented in this work. The proposed refreshing circuitry utilizes a voltage comparator to monitor the voltage drop caused by the data loss of a memory cell resulted from leakage currents to dynamically adjust the refreshing period of DRAM cells. A process variation monitor is also included in the proposed design to compensate the process drifting problem. Therefore, the proposed design is insensitive to temperature variations as well as process drifts. The period of the refreshing clock is automatically adjusted to save a great portion of standby power of DRAMs. A 4-Kb DRAM is implemented using a typical 0.13-£gm 1P8M digital CMOS process. Post-layout simulation results and a prototype on silicon justify the correctness of the adaptive refreshing cycles generated by the proposed design. In the second topic, a high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an Error Amplifier, the independence of off-chip capacitor and ESR is ensured for different load currents and operating voltages. Therefore, in low Iddq or low voltage scenarios, the total error of the output voltage caused by line and load variations is less than ¡Ó3% according to the on-silicon measurement results.

Sense amplifiers are important circuit components of a dynamic random access memory (DRAM), which forms the main memory of digital computers. The ability of the sense amplifier to detect and amplify voltage signals to correctly interpret data in DRAM cells cannot be understated. The sense amplifier plays a significant role in the overall speed of the DRAM. Sense amplifiers require matched transistors for optimal performance. Hence, the effects of mismatch through process variations must be minimized. This thesis presents a research which leads to optimal nanoscale CMOS sense amplifiers by incorporating the effects of process variation early in the design process. The effects of process variation on the performance of a standard voltage sense amplifier, which is used in conventional DRAMs, is studied. Parametric analysis is performed through circuit simulations to investigate which parameters have the most impact on the performance of the sense amplifier. The figures-of-merit (FoMs) used to characterize the circuit are the precharge time, power dissipation, sense delay and sense margin. Statistical analysis is also performed to study the impact of process variations on each FoM. By analyzing the results from the statistical study, a method is presented to select parameter values that minimize the effects of process variation. A design flow algorithm incorporating dual oxide and dual threshold voltage based techniques is used to optimize the FoMs for the sense amplifier. Experimental results prove that the proposed approach improves precharge time by 83.9%, sense delay by 80.2% sense margin by 61.9%, and power dissipation by 13.1%.