The thesis is composed of two topics: a power-saving DRAMs with an adaptive refreshing clock generator, and a high precision low dropout regulator with nested feedback loops. In the first topic, an adaptive refreshing circuitry design for DRAMs is presented in this work. The proposed refreshing circuitry utilizes a voltage comparator to monitor the voltage drop caused by the data loss of a memory cell resulted from leakage currents to dynamically adjust the refreshing period of DRAM cells. A process variation monitor is also included in the proposed design to compensate the process drifting problem. Therefore, the proposed design is insensitive to temperature variations as well as process drifts. The period of the refreshing clock is automatically adjusted to save a great portion of standby power of DRAMs. A 4-Kb DRAM is implemented using a typical 0.13-£gm 1P8M digital CMOS process. Post-layout simulation results and a prototype on silicon justify the correctness of the adaptive refreshing cycles generated by the proposed design. In the second topic, a high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an Error Amplifier, the independence of off-chip capacitor and ESR is ensured for different load currents and operating voltages. Therefore, in low Iddq or low voltage scenarios, the total error of the output voltage caused by line and load variations is less than ¡Ó3% according to the on-silicon measurement results.