Power management has had an ever increasing role in the present electronic industry. Battery powered and handheld applications require power management techniques to extend the life of the battery and consequently the operation life of the device. Most systems incorporate several voltage regulators which supply various subsystems and provide isolation among such subsystems. Low dropout (LDO) voltage regulators are generally used to supply low voltage, low noise analog circuitry. Each LDO regulator demands a large external capacitor, in the range of a few microfarads, to perform. These external capacitors occupy valuable board space, increase the IC pin count, and prohibit system-on-chip (SoC) solutions. The presented research provides a solution to the present bulky external capacitor LDO voltage regulators with a capacitor-less LDO architecture. The large external capacitor was completely removed and replaced with a reasonable 100pF internal output capacitor, allowing for greater power system integration for SoC applications. A new compensation scheme is presented that provides both a fast transient response and full range ac stability from a 0mA to 50mA load current. A 50mA, 2.8V, capacitor-less LDO voltage regulator was fabricated in a TSMC 0.35um CMOS technology, consuming only 65uA of ground current with a dropout voltage of 200mV. Experimental results show that the proposed capacitor-less LDO voltage regulator exceeds the current published works in both transient response and ac stability. The architecture is also less sensitive to process variation and loading conditions. Thus, the presented capacitor-less LDO voltage regulator is suitable for SoC solutions.

To assess the performance and future possibilities of catalytic microwave pyrolysis, laboratory-scale experiments were conducted on a widely available biomass feedstock, Eucalyptus grandis. Non-catalysed microwave pyrolysis was conducted under varying conditions to determine important factors of the microwave pyrolysis process and to conduct a basic performance evaluation. Future possibilities of microwave pyrolysis were determined by comparison to available technologies. Calcined Mg-Al LDH clay (layered double oxide or LDO) was used as catalyst to improve the quality of the pyrolysis process and its products. The heating and reaction mechanisms for microwave pyrolysis show that it offers distinct advantages over conventional pyrolysis. The main advantages are rapid and efficient volumetric heating, as well as acceptable yields at lower temperatures (much lower than those required by conventional pyrolysis), which can possibly lead to significant energy savings. Comparing the performance of a modified domestic microwave to an off-the-shelf microwave unit (Roto Synth) proved that cheap and comparative microwave research is possible. The yields from the domestic microwave products compared very closely to those of the Roto Synth unit, each having yields for char, oil and gas of 47.9%, 33.2%, 18.9% and of 46.8%, 32.7%, 20.55% respectively. The cost of the modified domestic setup was ~1% of that of the off-the-shelf unit. The use of a quartz reactor and slight adjustments to the stepper motor driver and thermocouple are recommended for future use. The pyrolysis process was found to be very dependent on power and power density. Higher powers increase the liquid and gas yields and a critical power density was identified between 800W and 1000W. The effects of power density were interesting and led to conclusions regarding the penetration depth of microwaves which could possibly play a significant role in the scale-up of microwave pyrolysis technology. Microwave pyrolysis undeniably has several advantages over conventional pyrolysis. However, for it to become competitive, microwave fast pyrolysis technologies need to be developed through the use of mixed bed reactors that can achieve fast heating rates. Possible candidates include rotating cone and fluidised bed reactors. Hybrid technology also provides unique advantages and has huge potential. Comparison of pyrolysis technologies is difficult without good data on continuous microwave pyrolysis reactors, and therefore the development of such reactors is recommended for future research. Catalysis of microwave pyrolysis with LDO proved effective. The catalyst promoted the formation of volatiles (gas and liquid), even when present in small ratios. It also promoted the formation of esters and even anhydrides and small fractions of hydrocarbons at high catalyst ratios. The catalyst activity led to increased water yields. This indicated that it removes oxygen from the pyrolysis products, thereby improving their quality. The catalyst was believed to be limited by the low temperatures used in this investigation and higher temperatures might increase the release of CO2 and should be investigated. Significant reduction in the total acid number (TAN) and an improved dry-basis heating value were also achieved by the addition of the catalyst. The water content increased from 50% to 70%, the TAN reduced from 174 mg KOH/(g oil) to 72 mg KOH/(g oil), and the calorific value increased from 19.1 MJ/kg to 21.5 MJ/kg. / Dissertation (MEng)--University of Pretoria, 2017. / Chemical Engineering / MEng / Unrestricted

Ce travail concerne l'étude et la réalisation de stratégies d'auto-test intégrées pour VCO radiofréquence (RF). La complexité des circuits intégrés RF devient un obstacle pour la mesure des principaux blocs RF des chaines de transmission/réception. Certains nœuds ne sont pas accessibles, l'excursion en tension des signaux baisse et les signaux haute fréquence ne peuvent pas être amenés à l'extérieur de la puce sans une forte dégradation. Le s techniques habituelles de test deviennent très couteuses et lentes. Le test pour le wafer-sort est étudié en premier. La solution proposée est la mise en œuvre d'une stratégie d'auto-test intégrée (BIST) qui puisse discriminer entre circuits sans fautes et circuits avec fautes pendant le wafer-test. La méthodologie utilisée est le test structurel. La couverture des fautes est étudiée pour connaitre la quantité à capter au niveau intégré afin de maximiser la probabilité de trouver tous les défauts physiques dans le VCO. Le résultat de cette analyse montre que la couverture des fautes est maximisée quand la tension crête-crête en sortie du VCO est captée. La caractérisation complète (validation de la puce et process-monitoring) du VCO est étudiée dans la deuxième étape. Les informations à extraire de la puce sont: amplitude des signaux, consommation du VCO, fréquence d'oscillation, gain de conversion (Kvco) et une information à propos du bruit de phase. Un démonstrateur pour le test au niveau wafer est réalisé en technologie ST CMOS 65nm. Le démonstrateur est composé d'un VCO 3.5GHz (le circuit sous test), un LDO, une référence de tension indépendante de température et variations d'alimentation, un capteur de tension crête-crête et un comparateur. Le capteur Vpp donne en sortie une information DC qui est comparée avec une plage de valeurs acceptables. Le BIST donne en sortie une information numérique pass/fail. / This work deals with the study and the realization of Built-In Self-Tests (BIST) for RF VCOs (Voltage Controlled Oscillators) The increasing complexity of RF integrated circuits is creating an obstacle for the correct measurement of the main RF blocks of any transceiver. Some nodes are not accessible, the voltage excursion of the signals is getting lower and lower and high frequency signals cannot be driven off the die without a main degradation. The common test techniques become then very expensive and time consuming. The wafer sort is firstly approached. The proposed solution is the implementation of a BIST strategy able to discriminate between faulty and good circuits during the wafer test. The chosen methodology is the structural test (fault-oriented). A fault coverage campaign is carried out in order to find the quantity to monitor on-chip that maximizes the probability to find all possible physical defects in the VCO. The result of the analysis reveals that the fault coverage is maximized if the peak-to-peak output voltage is monitored. The complete on-chip characterization of the VCO is then addressed, for chip validation and process monitoring. The information that need to be extracted on-chip concern: amplitude of the signal, consumption of the VCO, frequency of oscillation, its conversion gain (voltage-to-frequency) and eventually some information on the phase noise. A silicon demonstrator for wafer sort purposes is implemented using the ST CMOS 65nm process. It includes a 3.5GHz VCO, an LDO, a temperature and supply-voltage independent voltage reference, a peak-to-peak voltage detector and a comparator. The Vpp detector outputs a DC-voltage that is compared to a predefined acceptance boundary. A logic pass/fail signal is output by the BIST. The attention is then turned to the study of the proposed architecture for an on-chip frequency-meter able to measure the RF frequency with high accuracy. Behavioral simulations using VHDL-AMS lead to the conclusion that a TDC (Time-to-Digital Converter) is the best solution for our goal. The road is then opened to the measure of long-time jitter making use of the same TDC.

abstract: The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task. The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

abstract: Modern day deep sub-micron SOC architectures often demand very low supply noise levels. As supply voltage decreases with decreasing deep sub-micron gate length, noise on the power supply starts playing a dominant role in noise-sensitive analog blocks, especially high precision ADC, PLL, and RF SOC's. Most handheld and portable applications and highly sensitive medical instrumentation circuits tend to use low noise regulators as on-chip or on board power supply. Nonlinearities associated with LNA's, mixers and oscillators up-convert low frequency noise with the signal band. Specifically, synthesizer and TCXO phase noise, LNA and mixer noise figure, and adjacent channel power ratios of the PA are heavily influenced by the supply noise and ripple. This poses a stringent requirement on a very low noise power supply with high accuracy and fast transient response. Low Dropout (LDO) regulators are preferred over switching regulators for these applications due to their attractive low noise and low ripple features. LDO's shield sensitive blocks from high frequency fluctuations on the power supply while providing high accuracy, fast response supply regulation. This research focuses on developing innovative techniques to reduce the noise of any generic wideband LDO, stable with or without load capacitor. The proposed techniques include Switched RC Filtering to reduce the Bandgap Reference noise, Current Mode Chopping to reduce the Error Amplifier noise & MOS-R based RC filter to reduce the noise due to bias current. The residual chopping ripple was reduced using a Switched Capacitor notch filter. Using these techniques, the integrated noise of a wideband LDO was brought down to 15µV in the integration band of 10Hz to 100kHz. These techniques can be integrated into any generic LDO without any significant area overhead. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

abstract: With the push for integration, a slew of modern switching power management circuits are operating at higher switching frequencies in order to reduce passive filter sizes. But while these switching regulators provide power conversion at high efficiencies, their output is prone to ripples due to the inherent switching behavior. These switching regulators use linear-low dropout regulators (LDOs) downstream to provide clean supplies. Typically, these LDOs have good power supply rejection (PSR) at lower frequencies but this degrades at higher frequencies. Therefore, some residual ripple is still manifested on the output. Because of this, high power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems- on-chip (SOCs). Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop- bandwidth. The LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system- level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1μs and has a quiescent current of 5.6μA. For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 mV and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2020

abstract: Power management circuits are employed in most electronic integrated systems, including applications for automotive, IoT, and smart wearables. Oftentimes, these power management circuits become a single point of system failure, and since they are present in most modern electronic devices, they become a target for hardware security attacks. Digital circuits are typically more prone to security attacks compared to analog circuits, but malfunctions in digital circuitry can affect the analog performance/parameters of power management circuits. This research studies the effect that these hacks will have on the analog performance of power circuits, specifically linear and switching power regulators/converters. Apart from security attacks, these circuits suffer from performance degradations due to temperature, aging, and load stress. Power management circuits usually consist of regulators or converters that regulate the load’s voltage supply by employing a feedback loop, and the stability of the feedback loop is a critical parameter in the system design. Oftentimes, the passive components employed in these circuits shift in value over varying conditions and may cause instability within the power converter. Therefore, variations in the passive components, as well as malicious hardware security attacks, can degrade regulator performance and affect the system’s stability. The traditional ways of detecting phase margin, which indicates system stability, employ techniques that require the converter to be in open loop, and hence can’t be used while the system is deployed in-the-field under normal operation. Aging of components and security attacks may occur after the power management systems have completed post-production test and have been deployed, and they may not cause catastrophic failure of the system, hence making them difficult to detect. These two issues of component variations and security attacks can be detected during normal operation over the product lifetime, if the frequency response of the power converter can be monitored in-situ and in-field. This work presents a method to monitor the phase margin (stability) of a power converter without affecting its normal mode of operation by injecting a white noise/ pseudo random binary sequence (PRBS). Furthermore, this work investigates the analog performance parameters, including phase margin, that are affected by various digital hacks on the control circuitry associated with power converters. A case study of potential hardware attacks is completed for a linear low-dropout regulator (LDO). / Dissertation/Thesis / Masters Thesis Electrical Engineering 2019

Submitted by Mario Filho (magoamfi@ig.com.br) on 2014-07-12T03:49:21Z No. of bitstreams: 1 Disseração Mestrado.pdf: 1221977 bytes, checksum: 0f96be6dae8a0041fa9b8671f9c114dd (MD5) / Approved for entry into archive by Janete de Oliveira Feitosa (janete.feitosa@fgv.br) on 2014-07-16T16:48:20Z (GMT) No. of bitstreams: 1 Disseração Mestrado.pdf: 1221977 bytes, checksum: 0f96be6dae8a0041fa9b8671f9c114dd (MD5) / Approved for entry into archive by Marcia Bacha (marcia.bacha@fgv.br) on 2014-07-18T12:03:17Z (GMT) No. of bitstreams: 1 Disseração Mestrado.pdf: 1221977 bytes, checksum: 0f96be6dae8a0041fa9b8671f9c114dd (MD5) / Made available in DSpace on 2014-07-18T12:03:27Z (GMT). No. of bitstreams: 1 Disseração Mestrado.pdf: 1221977 bytes, checksum: 0f96be6dae8a0041fa9b8671f9c114dd (MD5) Previous issue date: 2014-05-22 / The objective of this work is to identify the factors that influenced the attempt to transpose the campaign promises of major election for mayor of Nilópolis in the 2012 election for the PPA 2014 / 2017 . For this, the concepts of federalism , public management and planning tools were discussed in the theoretical framework. Interviews with technical and executive manager , the chairmen of the constitution and justice and the finance committee were held , as well as president of the city council of Nilópolis. It was found that the factors identified are responsible for the difficulty in promoting alignment between campaign promises and agreed in the PPA . The dependence of inter -governmental transfers and the scarcity of resources were the main factors that hindered implementation in the municipality of Nilópolis. / O objetivo deste trabalho é de identificar os fatores que influenciaram a tentativa de transpor as promessas de campanha da eleição majoritária à Prefeitura de Nilópolis na eleição de 2012 para o PPA 2014 / 2017. Para isso, os conceitos de federalismo, gestão pública e instrumentos de planejamento foram abordados no referencial teórico. Foram realizadas entrevistas com os técnicos e o gestor do executivo, os presidentes das comissões de constituição e justiça e comissão de finanças, bem como o presidente da câmara dos vereadores de Nilópolis. Verificou-se que os fatores identificados são responsáveis pela dificuldade em promover o alinhamento entre as promessas de campanha e o pactuado no PPA. A dependência das transferências inter governamentais e a escassez de recursos próprios foram os principais fatores que dificultaram essa transposição no município de Nilópolis.

The objective of this dissertation is to develop key components of a CMOS heterodyne millimeter-wave receiver front end. Robust designs are necessary to overcome PVT variations as well as modeling inaccuracies, while with minimum power consumption overhead to facilitate low-power radio for portable applications. Heterodyne receiver topology is adopted because of its robust performances at millimeter-wave frequencies. Device models for both passive and active devices are developed and used in the circuit designs in this dissertation. Two low-noise amplifiers (LNAs) are developed in this dissertation. The first LNA features a proposed temperature-compensation biasing technique, which confines the gain variation within 5 dB for temperature variation from -5 to 85 Celsius degree. The measured gain and NF are 21 and 6.5 dB, respectively, for 49-mW power dissipation. The second LNA reveals a design technique to tolerate a low-accuracy model at millimeter-wave frequencies. Both LNAs provide full coverage of the FCC 60-GHz band (57-64 GHz). For the frequency generation circuits, both the IF QVCO and mm-wave VCO are investigated. The inherent bimodal oscillation of QVCOs is analyzed and, for the first time, a systematic measurement technique is proposed to intentionally control the oscillation mode. This technique is further utilized to extend the tuning range of the QVCO, which possesses dual tuning curves without penalty on phase noise. The measurement results of a 13-GHz QVCO in 90-nm CMOS reveals a 21.4% tuning range for continuously tuning from 11.7 to 14.5 GHz. The measured phase noise is -108 dBc/Hz at 1 MHz offset with a core power consumption of 10.8 mW. A millimeter-wave VCO is designed and fabricated in 65-nm CMOS. The VCO is fully characterized under voltage stress to examine the hot-carrier injection effects affecting the performance of a millimeter-wave VCO. The 41.6-47.4 GHz VCO is further integrated into a millimeter-wave down converter. The power-hungry buffer amplifiers are neglected by proper floor planning. Conversion loss of 1.4 dB is obtained with total power consumption of 72.5 mW. Lastly, a power management system consisting of low-dropout (LDO) regulators is designed and integrated in a 90-nm CMOS millimeter-wave transceiver to provide stable and low-noise supply voltages. Voltage variation issues are alleviated by the LDOs.

Power management components can be found in a host of different applications ranging from portable hand held gadgets to modern avionics to advanced medical instrumentations, among many other applications. Low-dropout (LDO) linear regulators are particularly popular owing to their: ease of use, low cost, high accuracy, low noise, and high bandwidth. With all its glory, however, it tends to underperform switched-mode power supplies (SMPS) when with comes to power conversion efficiency, although the later generates a lot of ripple at its output. With the growing need to improve system efficiency (hence longer battery life) without degrading system performance, many high end (noise sensitive) applications such as data converters, RF transceivers, precision signal conditioning, among others, use high efficiency SMPS with LDO regulators as post-regulators for rejecting the ripple generated by SMPS. This attribute of LDO regulators is known as power supply rejection (PSR). With the trend towards increasing switching frequency for SMPS, to minimize PC board real estate, it is becoming ever more difficult for LDO regulators to suppress the associate high frequency ripple since at such high frequencies, different parasitic components of the LDO regulator start to deteriorate its PSR performance. There have been a handful of different techniques suggested in the literature that can be used to achieve good PSR performance at higher frequencies. However, each of these techniques suffers from a number of drawbacks ranging from reduced efficiency to increased cost to increased solution size, and with the growing demand for higher efficiency and smaller power supplies, these techniques have their clear limitations. The objective of this research project is to develop a novel current-mode LDO regulator that can achieve good high frequency PSR performance without suffering from the afore mentioned drawbacks. The proposed architecture was fabricated using a proprietary 1.5 um Bipolar process technology, and the measurement results show a PSR improvement of 20dB (at high frequencies) over conventional regulators. Moreover, the proposed LDO regulator requires a small 15nF output capacitor for stability, which is far smaller than some of the currently used techniques.