Low-swing on-chip interconnect circuits have been viewed as alternative solutions to the problem of delay and power increase of on-chip interconnects. This thesis aims to characterize and optimize several basic low-swing interconnect circuits, by developing simple delay and power estimation methodologies. Accuracies of the proposed methods are validated against SPICE-based simulations on the 90nm technology node. Based on the delay and power estimation methods developed, optimum power-delay trade-off curves are obtained and directly used for comparison among different interconnect circuit strategies. Three low-swing techniques are included, i.e. conventional level converter (CLC), pseudodifferential interconnect circuit (PDIFF), and current-mode signaling (CM). These techniques represent significantly different driver and receiver topologies, where CLC uses lower supply voltage of a normal inverter driver, PDIFF uses NMOS only drivers, while CM has a low impedance termination at the receiving end. In addition, an optimized full-swing repeater-based technique is included as a baseline for comparison. A simplified repeater performance estimation technique considering ramp input signals is also proposed. The most important step in estimating delay of different driver circuits is the accurate estimation of transistor effective resistance, which considers velocity saturation effects and voltage transition patterns. Optimization for the CM circuit for on-chip interconnects requires completely different treatment than the voltage-mode circuits, due to the different and more complex effective driver resistance and termination resistance modeling. Sizing the driver and receiver transistors should be done simultaneously as their resistive values which affect its performance are dependent on each other. Optimum transistor sizing is very dependenton the required voltage swing chosen. Results of our comparisons show that optimized CLC (reduced voltage supply) repeaters appears to give the best general performance with a slight delay overhead compared to full-swing repeaters. The fact that CLC with repeaters has shorter delay than single-segment CM and PDIFF highlights the effectiveness of repeater structures in long wires. The inclusion of inductance and closed-form solutions to derive optimum transistor sizings for various low-swing interconnect circuits may be developed as a future work using delay and power estimation models presented in this thesis, which is a challenging task to do considering the non-linear equations involved.

This thesis aims at investigating the technologies of the active power-factor correction (PFC) circuit. The system originally in the article is based on a boost converter circuit as the structure, the control method is to adopt the average current mode. We doesn¡¦t only narrate the circuit principle of the systematic circuit in the article but also use the OrCAD PSpice A/D software to simulation. Finally, we implemented make a prototype circuit and verified the proposed method. The experimental result shows that it can reach the goal for the power-factor correction.

The thesis begins with a review of presently available analogue and digital control schemes for high frequency PWM converters. Advantages and disadvantages of each scheme are identified, to determine which features would be desirable in a new digital control scheme. An extensive examination of peak and average current mode control is undertaken, using state-space/sampled data modelling, to gain more detailed information on the properties of current mode control. On the basis of this information, a new digital current mode control scheme is put forward. This uses samples of the inductor current, line voltage and output voltage to implement a control strategy in software. Average inductor current is calculated each switching cycle and compared to the current program level, providing true current mode control. This has some advantages over traditional methods. Accurate inductor current tracking of the current program level is achieved and no slope compensation is required for stable operation over the full range of duty ratios. Line voltage feed-forward is possible in buck derived topologies, which provides an effective null in the audio susceptibility transfer function, independent of compensation parameters. Current loop stability is independent of line voltage or load current in the buck topology, allowing operation with optimum loop compensation under all normal operating conditions. Practical implementation of a digital current mode controlled current-fed converter is described. This includes a modular architecture for the hardware and documentation for the software. Effects of component selection on the achievable converter switching frequency and dynamic performance are discussed. A method is put forward for the direct digital measurement of loop gain and phase in digital control systems. This is used to obtain actual loop responses from a test bed digital current mode controlled current-fed converter. Line and load transient response tests are presented which demonstrate the dynamic characteristics of digital current mode control.

A low-energy current-mode algorithmic pipelined ADC targeted for use in distributed sensor networks is presented. The individual nodes combine sensing, computation and communications into an extremely small volume. The nodes operate with very low duty cycle due to limited energy. Ideally these sensor networks will be massive in size and dense in order to promote redundancy. In addition the networks will be collectively intelligent and adaptive. To achieve these goals, distributed sensor networks will require very small,inexpensive nodes that run for long periods of time on very little energy. One component of such network nodes is an A/D converter. An ADC acts as a crucial interface between the sensed environment and the sensor network as a whole. The work presented here focuses on moderate resolution, and moderate speed, but ultra-low-power ADCs. The 6 bit current-mode algorithmic pipelined ADC reported here consumes 8 pJ/bit samples at 0.65V supply and 130 kS/s. The current was chosen as the information carrying quantity instead of voltage as it is more favorable for low-voltage and low-power applications. The reference current chosen was 150nA. All the blocks are using transistors operating in subthreshold or weak inversion region of operation, to work in low-voltage and low current supply. The DNL and INL plots are given in simulation results section. The area of the overall ADC was 0.046 mm2 only.

abstract: During the past decade, different kinds of fancy functions are developed in portable electronic devices. This trend triggers the research of how to enhance battery lifetime to meet the requirement of fast growing demand of power in portable devices. DC-DC converter is the connection configuration between the battery and the functional circuitry. A good design of DC-DC converter will maximize the power efficiency and stabilize the power supply of following stages. As the representative of the DC-DC converter, Buck converter, which is a step down DC-DC converter that the output voltage level is smaller than the input voltage level, is the best-fit sample to start with. Digital control for DC-DC converters reduces noise sensitivity and enhances process, voltage and temperature (PVT) tolerance compared with analog control method. Also it will reduce the chip area and cost correspondingly. In battery-friendly perspective, current mode control has its advantage in over-current protection and parallel current sharing, which can form different structures to extend battery lifetime. In the thesis, the method to implement digitally average current mode control is introduced; including the FPGA based digital controller design flow. Based on the behavioral model of the close loop Buck converter with digital current control, the first FPGA based average current mode controller is burned into board and tested. With the analysis, the design metric of average current mode control is provided in the study. This will be the guideline of the parallel structure of future research. / Dissertation/Thesis / M.S. Electrical Engineering 2011

Threshold logic gates are gaining more importance in recent years due to significant development in switching devices. This renewed the interest in high performance and low power circuits with threshold logic gates. Threshold Logic Gates can be implemented using both the traditional CMOS technologies and the emerging nanoelectronic technologies. In this dissertation, we have performed performance analysis on Monostable-Bistable Threshold Logic Element based, current mode, and memristor based threshold logic implementations. Existing analytical approaches that model the delay of a Monostable-Bistable Threshold Logic Element threshold logic gate cannot explore the enormous search space in the quest of weight assignments on the inputs and threshold in order to optimize the delay of the threshold logic gate. It is shown that this can be achieved by using a quantity that depends on the constants and Resonant Tunnel Diode weights. This quantity is used to form an integer linear program that optimizes the performance and ensure that each weight can tolerate a predetermined variation by an appropriate weight assignment in a threshold logic gate. The presented experimental results demonstrate the impact of the proposed method. The optimality of our solutions and the reported improvements ensure tolerance to potential manufacturing defects. Current mode is a popular CMOS-based implementation of threshold logic functions where the gate delay depends on the sensor size. A new implementation of current mode threshold functions for improved performance and switching energy is presented. An analytical method is also proposed in order to identify quickly the optimum sensor size. Experimental results on different gates with the optimum sensor size indicate that the proposed method outperforms consistently the existing implementations, and implements high performance and low power gates that have a very large number of inputs. A new dual clocked design that uses memristors in current mode logic implementation of threshold logic gates is also presented. Memristor based designs have high potential to improve performance and energy over purely CMOS-based combinational methods. The proposed designs are clocked, and outperform a recently proposed combinational method in performance as well as energy consumption. It is experimentally verified that both designs scale well in both energy consumption as well as delay.

This master´s thesis deals about a measuring structures of elements working at a current mode. There were outlined structures for measuring input and output impedance. These structures were simulated for DACA element. It deals with a voltage to current and current to voltage converters. All structures and converters were simulated at computer program PSpice. Selected variant were practically verified and control measuring was realized.

This thesis presents the fundamental issues of the digital controlled DC/DC converter. A lot of challenges exist when you introduce the digital control technique into the control of the DC/DC converter, especially with regards to the voltage regulator module. One issue is the limit cycle oscillation problem caused by the quantization effect from the ADC and DPWM of the digital control chip. Another issue is the delay problem coming from the sample-hold effect. In this thesis, the modeling, analysis and design methodology for the constant frequency voltage-mode control is reviewed. A DPWM (Digital Pulse Width Modulator) model is verified in simulation, which shows what effects the digital control brings to the conventional Pulse Width Modulator. In CPES, the constant on-time control concept is introduced into the digital control of the voltage regulator module. This provides a high resolution of DPWM and allows the digital constant on-time voltage-mode control architecture to be proposed. To limit the oscillation amplitude in the digital control structure, the digital constant on-time current-mode control w/ external ramp is further proposed in CPES. To analyze this structure, a describing function model is proposed for the digital constant on-time current-mode control, which takes both the sample-hold effect and the quantization effect into consideration. This model clearly shows the stability problem caused by the sample-hold effect in the current loop. Using larger ramp's slope values, this stability issue can be alleviated. Based on this model, a design methodology is introduced. By properly designing the current loop's ADC resolution and the voltage loop's ADC resolution, the limit cycle oscillation in this structure can be minimized: the digital constant on-time current-mode control will only have the oscillation coming from the sample-hold effect in the current loop, which can be greatly reduced by adding the large slope's external ramp to this structure. Simulation verification for this design methodology is provided to prove the concepts. Based on the proposed model, the compensator design is performed. The motivation for the compensator design is to push the bandwidth while satisfying the stability condition and the dynamic no-limit-cycle oscillation condition. When analyzing the case of one sample per switching cycle, there is a certain amount of delay, which compromises the phase characteristics. Our design also requires a large external ramp because it will reduce the oscillation amplitude in our system. From our model, it is quite obvious that the external ramp must have a slope larger than one time that of inductor current down slope. A slope that is too larger will weaker the phase and limit the bandwidth. When using the normal current-mode compensator, like the 1-pole 1-zero compensator, the phase is dropped too much and the bandwidth will be limited too low. If we use a 2-pole 2-zero compensator, the phase can be boosted. However, in this case, the gain margin requirement from the dynamic no-limit-cycle oscillation condition will make the further improvements on bandwidth impossible. In our design, the one sixth of the switching frequency is achieved. / Master of Science

Current-mode control architectures with different implementation approaches have been an indispensable technique in many applications, such as voltage regulator, power factor correction, battery charger and LED driver. Since the inductor current ramp, one of state variables influenced by the input voltage and the output voltage, is used in the modulator in current-mode control without any low pass filter, high order harmonics play important role in the feedback control. This is the reason for the difficulty in obtaining the small-signal model for current-mode control in the frequency domain. A continuous time domain model was recently proposed as a successful model for current-mode control architectures with different implementation. However, the model was derived by describing function method, which is very arithmatically complicated, not to mention time consuming. Although an equivalent circuit for a current mode control Buck converter was proposed to help designers to use the model without involving complicated math, the equivalent circuit is not a complete model. Moreover, no equivalent circuit for other topologies is available for designers. In this thesis, the primary objective is to develop a unified three-terminal switch model for current-mode control with different implementation methods, which are applicable in all the current mode control power converters. First, the existing model for current mode control is reviewed. The limitation of average models and the discrete time model for current-mode control is identified. The continuous time model and its equivalent circuit of Buck converter is introduced. The deficiency of the equivalent circuit is discussed. After that, a unified three-terminal switch model for current mode control is presented. Based on the observation, the PWM switch and the closed current loop is taken as an invariant sub-circuit which is common to different DC/DC converter topologies. A basic small signal relationship between terminal currents is studied and the result shows that the PWM switch with current feedback preserves the property of the PWM switch in power stage. A three-terminal equivalent circuit is developed to represent the small signal behavior of this common sub-circuit. The proposed model is a unified model, which is applicable in both constant frequency modulation and variable frequency modulation. The physical meaning of the three-terminal equivalent circuit model is discussed. The model is verified by SIMPLIS simulation in commonly used converters for both constant frequency modulation and variable frequency modulation. Then, based on the proposed unified model, a comparison between different current mode control implementations is presented. In different applications, different implementations have their unique benefit on extending control bandwidth. The properties of audio susceptibility and output impedance are discussed. It is found that, for adaptive voltage positioning design, constant on-time current mode control can simplifies the outer loop design. Next, since multiphase interleaving structure is widely used in PFC, voltage regulator and other high current applications, the model is extended to multiphase current mode control. Some design concerns are discussed based on the model. As a conclusion, a unified three-terminal switch model for current mode controls is investigated. The proposed model is quite general and not limited by implementation methods and topologies. All the modeling results are verified through simulation and experiments. / Master of Science

Current-mode control architectures have been an indispensable technique in many applications, such as Voltage Regulator, Point-of-load converters, power factor correction, battery charger and LED driver. Since the inductor current ramp is used in the modulator in current-mode control without any low pass filter, high order harmonics play important role in the feedback control. This is the reason for the difficulty in obtaining the small-signal model for current-mode control in the frequency domain. A continuous time domain model was recently proposed as a successful model for current-mode control architectures. However, the model was derived by describing function method, which is very arithmetically complicated, not to mention time consuming. For the analysis and design of non-linear system, equivalent circuit model, which is user friendly and intuitive, is an effective tool. In this dissertation, the primary objective is to develop a unified three-terminal switch model for current-mode controls using the results of describing function derivation, which characterizes the small signal property of the common subcircuit of current mode controlled PWM converters. Its application is extended to average current mode control, V2 control and other proposed novel current mode control schemes. First, the existing model for current mode control is reviewed. The limitations of existing model for current-mode control are identified. Based on the universal small signal relationship between terminal currents and the results of describing function derivation, a unified three-terminal switch model for current mode control is proposed. A three-terminal equivalent circuit is developed to represent the small signal behavior of this common sub-circuit. The proposed model is applicable in both constant frequency and variable frequency modulation. After that, the modeling of digital predictive current mode control is presented. Predictive current mode control is one of the promising digital current mode control method featuring fast dynamic response and low sample rate requirement. Many implementations were presented in past ten years. To understand the benefit and the limitation of each implementation, help the engineer to choose the modulation scheme and design the control loop, a small signal Laplace-domain model for digital predictive current mode controls is proposed. The model is extended to the multi-sampled implementation. The modeling result is summarize as the small signal equivalent circuit mode, whose form is consistent with that of analog current mode controls. Based on S-domain model, digital predictive current mode controls are compared with analog implementation to demonstrate the advantages and limitation. Implementation selection guideline and compensation is discussed based on the modeling results. Then, using the proposed unified model is used in the analysis of average current mode control. Under proper design, the inductor current ripple passes through the current compensator and appears in PWM comparator. It significantly influence the high frequency small signal property of the converter. In chapter 3, the proportional feedback is separated from integral feedback so that the sideband frequency feedback effect can be taken into consideration. It extends the results obtained in peak-current model control to average current mode control. The proposed small signal model is accurate up to half switching frequency, predicting the sub-harmonic instability. Based on the proposed model, a new feedback design guideline is proposed. By designing the external ramp following the proposed design guideline, quality factor of the double poles at half of switching frequency in control-to-output transfer function can be precisely controlled. This helps the feedback design to achieve widest control bandwidth and proper damping. V2 control is a popular control scheme in Point-of-load converters due to the unique fast transient response. As the output voltage ripple is used as PWM modulation ramp, V2 control has close relationship with current mode control but this relationship was not addressed in the existing model. Chapter 4 utilizes the three-terminal switch model to build the equivalent circuit model for V2 control, which clearly shows that V2 control is a particular implementation of current mode control, with proportional capacitor voltage feedback and load current feedback embedded. The analysis presented in Chapter 3 provides a clear physical understanding of average current mode control. With constant frequency modulation, the control bandwidth is usually limited by the double pole at half of swithcing frequency, especially in the converters with wide duty cycle range. Chapter 5 proposed a novel I2 current mode control to improve the dynamic performance of average current mode control. In particular, constant on-time I2 control eliminates the need of external ramp while the current loop is inherently stable. Moreover, constant on-time modulation improves the light load efficiency. As a conclusion, this dissertation proposed a unified three-terminal switch model for current mode controls. The application of this equivalent circuit model is extended to average current mode control, V2 control and the novel I2 current mode control. The Laplace-domain model of predictive current mode control is also presented. All the modeling results are verified through simulation and experiments. / Ph. D.