Low-swing on-chip interconnect circuits have been viewed as alternative solutions to the problem of delay and power increase of on-chip interconnects. This thesis aims to characterize and optimize several basic low-swing interconnect circuits, by developing simple delay and power estimation methodologies. Accuracies of the proposed methods are validated against SPICE-based simulations on the 90nm technology node. Based on the delay and power estimation methods developed, optimum power-delay trade-off curves are obtained and directly used for comparison among different interconnect circuit strategies. Three low-swing techniques are included, i.e. conventional level converter (CLC), pseudodifferential interconnect circuit (PDIFF), and current-mode signaling (CM). These techniques represent significantly different driver and receiver topologies, where CLC uses lower supply voltage of a normal inverter driver, PDIFF uses NMOS only drivers, while CM has a low impedance termination at the receiving end. In addition, an optimized full-swing repeater-based technique is included as a baseline for comparison. A simplified repeater performance estimation technique considering ramp input signals is also proposed. The most important step in estimating delay of different driver circuits is the accurate estimation of transistor effective resistance, which considers velocity saturation effects and voltage transition patterns. Optimization for the CM circuit for on-chip interconnects requires completely different treatment than the voltage-mode circuits, due to the different and more complex effective driver resistance and termination resistance modeling. Sizing the driver and receiver transistors should be done simultaneously as their resistive values which affect its performance are dependent on each other. Optimum transistor sizing is very dependenton the required voltage swing chosen. Results of our comparisons show that optimized CLC (reduced voltage supply) repeaters appears to give the best general performance with a slight delay overhead compared to full-swing repeaters. The fact that CLC with repeaters has shorter delay than single-segment CM and PDIFF highlights the effectiveness of repeater structures in long wires. The inclusion of inductance and closed-form solutions to derive optimum transistor sizings for various low-swing interconnect circuits may be developed as a future work using delay and power estimation models presented in this thesis, which is a challenging task to do considering the non-linear equations involved.

The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. Rapid progress in silicon VLSI technologies has made it possible to implement multi-function and high performance electronic circuits on a single die. Coupled with this, the need for interfacing digital blocks to the external world resulted in the integration of analog blocks such as A/D and D/A converters, filters and oscillators with the digital logic on the same die. Thus, mixed signal system-on-chip (SOC) solutions are becoming a common practice in the present day integrated circuit (IC) technologies. In digital domain, aggressive technology scaling redefines, in many ways, the role of interconnects vis-`a-vis the logic in determining the overall performance. Apart from signal integrity, power dissipation and reliability issues, delays over long interconnects far exceeding the logic delay becomes a bottleneck in high speed operation. Moreover, with an increasing density of chips, the number of interchip connections is greatly increased as more and more functions are put on the same chip; thus, the size and performance of the chip are mostly dominated by wiring rather than devices. One of the most promising approaches to solve the above interconnection problems is the use of multiple-valued logic (MVL) inside the chip [Han93, Smi88]. The number of interconnections can be directly reduced with multiple valued signal representation. The reduced complexity of interconnections makes the chip area and delay much smaller leading to reduced cross talk noise and improved reliability. Thus, the inclusion of multiple-valued logic in a otherwise mixed design, consisting of analog and binary logic, can make the transition from analog to digital world much more smoother and at the same time improve the overall system performance. As the sizes of integrated devices decrease, maximum voltage ratings also rapidly decrease. Although decreased supply voltages do not restrict the design of digital circuits, it is harder to design high performance analog and multiple valued integrated circuits using new processes. As an alternative to voltage-mode signal processing, current-mode circuit techniques, which use current as a signal carrier, are drawing strong attention today due to their potential application in the design of high-speed mixed-signal processing circuits in low-voltage standard VLSI CMOS technologies. Industrial interest in this field has been propelled by the proposal of innovative ideas for filters, data converters and IC prototypes in the high frequency range [Tou90, Kol00]. Further, in MVL design using conventional CMOS processing, different current levels can be easily used to represent different logic values. Thus the case for an integrated approach to the design of analog, multi-valued and binary logic circuits using current-mode techniques seems to be worth considering. The work presented in this thesis is an effort to reaffirm the utility of current-mode circuit techniques to some of the existing as well as to some new areas of circuit design. We present new algorithms for the synthesis of a class of analog and multiple-valued logic circuits assuming an underlying CMOS current-mode building blocks. Next we present quaternary current-mode signaling scheme employing a simple encoder and decoder architecture for improving the signal delay characteristics of long interconnects in digital logic blocks. As an interface between analog and digital domain, we present an architecture of current-mode flash A/D converter. Finally, low power being a dominant design constraint in today IC technology, we present a scheme for static power minimization in a class of Current-mode circuits.