This thesis includes two research topics. The first topic is a linear LDO regulator. The second one is a low noise amplifier (LNA). Both of the circuits can be applied to a totally implantable micro-electrical neural interfacing SOC.
The linear LDO regulator is enhanced with a novel compensation technology, called modified NMCF (nested Miller compensation with feedforward Gm stage), resulting in that its performance is independent of the off-chip capacitor and its ESR (equivalent series resistor). The proposed compensation method ensures the stability of the feedback loop and the large enough phase margin of the LDO (low dropout) regulator. The power supply rejection ratio is 30 dB (operating at [200 Hz, 3 MHz] and a load of [50
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0705105-233301 |
| Date | 05 July 2005 |
| Creators | Huang, Chi-chun |
| Contributors | Jyy-Sheng Hong, Chua-chin Wang, Jih-Ching Chiu, Sying-jyan Wang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0705105-233301 |
| Rights | not_available, Copyright information available at source archive |
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