Multi-phase Buck is widely used in Voltage Regulator Modules design because of its low cost and simplicity. But this topology also has a lot of drawbacks. One of the most fundamental drawback is that it has narrow duty cycles when it operates at high switching frequency with low output voltage (for example 1V). Narrow duty cycles yield high switching loss which limits the switching frequency of Buck; making it difficult to design a Buck based VRM that can achieve high efficiency at a high switching frequency. In this thesis three new non-isolated full bridge topologies will be introduced to solve the aforementioned problems of Buck. One is a new non-isolated full bridge topology, this new topology use a transformer to extend the duty cycle and it capable to achieve zero voltage switching. Experimental results demonstrate that it has significant advantages over multi-phase Buck. In some applications when huge output current is required, several converters are paralleled to supply the current that is not an optimal solution. Two two-phase non-isolated full bridge topologies are proposed to solve this problem. They double the output power of one-phase non-isolated full bridge, and achieve higher efficiency with fewer switches compared with parallel two non-isolated full bridge converters. Non-isolated VRM usually is used for personal computers, VRM for servers is called power pod, and usually isolation is required for power pod due to safety considerations. Server usually require much more power than personal computers, their power consumption is around several KW. To provide the power for the server a few power modules will need to be paralleled, this kind solution is expensive and make current sharing complex. In this thesis two new two-phase isolated full bridge topologies are proposed. They are capable to operate at soft switching mode. And they double the output power compared with conventional full bridge converter. Compared with parallel two full bridge converters, they can achieve higher efficiency with fewer switches. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2008-02-28 09:53:50.23

Advances in very large scale integration (VLSI) technologies impose challenges for voltage regulator modules (VRM) to deliver high-quality power to modern microprocessors. As an enabling technology, multiphase converters have become the standard practice in VRM industry. The primary objectives of this dissertation are to develop advanced topologies and innovative integrated magnetics for high-efficiency, high-power-density and fast-transient VRMs. The optimization of multiphase VRMs has also been addressed. Today's multiphase VRMs are almost universally based on the buck topology. With increased input voltage and decreased output voltage, the multiphase buck converter suffers from a very small duty cycle and cannot achieve a desirable efficiency. The multiphase tapped-inductor buck converter is one of the simplest topologies with a decent duty cycle. However, the leakage inductance of its tapped inductors causes a severe voltage spike problem. An improved topology, named the multiphase coupled-buck converter, is proposed. This innovative topology enables the use of a larger duty cycle with clamped device voltage and recovered leakage energy. Under the same transient responses, the multiphase coupled-buck converter has a significantly better efficiency than the multiphase buck converter. By integrating all the magnetic components into a single core, in which the windings are wound around the center leg and the air gaps are placed on the two outer legs, it is possible for multiphase VRMs to further improve efficiency and cut the size and cost. Unfortunately, this structure suffers from an undesirable core structure and huge leakage inductance. An improved integrated magnetic structure is proposed to overcome these limitations. All the windings are wound around the two outer legs and the air gap is placed on the center leg. The improved structure also features the flux ripple cancellation in the center leg and strongly reverse-coupled inductors. Both core loss and winding loss are reduced. The steady-state current ripples can be reduced without compromising the transient responses. The overall efficiency of the converter is improved. The input inductor can also be integrated in the improved integrated magnetic structure. Currently, selecting the appropriate number of channels for multiphase VRMs is still an empirical trial-and-error process. This dissertation proposes a methodology for determining the right number of channels for the optimal multiphase design. The problem formulation and general method for the optimization are proposed. Two examples are performed step by step to demonstrate the proposed optimization methodology. Both are focused on typical VRM 9.0 designs for the latest Pentium 4® microprocessors and their results are compared with the industry practice. / Ph. D.

It is perceived that Moore's Law will prevail at least for the next decade with the continuous advancement of processing technologies for integrated circuits. According to Intel's roadmap, over one billion transistors will be integrated in one processor by the year 2010; the processor's clock speed will approach 15 GHz; the core static currents will increase up to 200 A; the dynamic current slew rate will rise up to 250 A/ns; and the core voltage will decrease to 0.8 V. The rapid advancement of processor technology has posed stringent challenges to power management for both an efficient power delivery and an accurate voltage regulation. The primary objectives of this dissertation are to understand the fundamental limitations of the state-of-the-art solution for the power management, and hence to support possible solutions for meeting the power requirement of the next generations of processors. First, today's voltage-regulator module (VRM) design, which is based on the multiphase interleaving buck topology, is thoroughly analyzed. The analysis results of the control bandwidths versus the VRM transient voltage spikes highlight the trend of high-frequency VRM design for smaller size and faster transient response. Based on the concept of achieving constant VRM output impedance, design guidelines are proposed for different kinds of control methods. However, the high switching-related losses in the conventional multiphase buck converter limit its further applications. This dissertation proposes a series of new topologies in order to break through the barriers by applying an inductor-coupling or autotransformer structure to reduce the switching-related losses by extending the duty cycle. Then, this dissertation pushes the topology innovation further by introducing soft-switching quasi-resonant converters for the VRM design. The combination of the quasi-resonant and active-clamped concepts derives a family of new converters, which can eliminate all the switching and body-diode losses. The experimental results at 1-2MHz switching frequencies prove that the proposed solutions for the VRM design can realize very high efficiency and high power density. / Ph. D.

As a very special DC-DC converter, VRM (Voltage Regulator Module) design must follow the fast-developing trend of microprocessors. The design challenges are the high current, high di/dt, and stringent load-line requirement. When the energy is transferred from the input of a VRM, through the VRM, then through the power delivery path to the processor, it needs sufficient capacitors to relay this energy. The capacitors' number appears to be unrealistically large if we follow today's approach for the future processors. High frequency VRM with high control bandwidth can solve this problem, however, the degradation of efficiency makes the conventional buck converter and the hard-switching isolated topologies incapable of operating at higher frequency. The research goal is to develop novel means that can help a high-output- current VRM run efficiently at high frequency. A novel Complementary Controlled Bridge (CCB) self-driven concept is proposed. With the proposed self-driven scheme, the combination of the ZVS technique and the self-driven technique recycles the gate driving energy by making use of the input capacitor of the secondary- side synchronous rectifier (SR) as the snubber capacitor of the primary-side switches. Compared to the external driver, the proposed converter can save driving loss and synchronous rectifier body diode conduction loss. Additionally, compared to the existing level-shifted self-driven scheme for bridge-type symmetrical topologies, its gate signal ringing is small and suitable for high-frequency applications. Although the CCB self-driven VRM reduces the switching frequency-related losses significantly, the conduction loss is still high. Inspired by the current-doubler concept, a novel ZVS current-tripler DC-DC converter is proposed in this work. By utilizing more SR devices to share the current during the freewheeling period, the SR conduction loss is reduced. The current-tripler DC-DC converter has a delta/delta connected transformer that can be implemented with integrated magnetics. The transformer then becomes an integrated magnetic with distributed windings, which is preferred in high current applications. The current-tripler DC-DC converter in fact meets the requirements for the CCB self-driven scheme. The two concepts are then combined with an integrated gate drive transformer. The proposed CCB self-driven concept and current-tripler concept can both be applied to the 12V non-isolated VRMs. The proposed topology is basically a buck-derived soft-switching topology with duty cycle extension and SR device self-driven capabilities. Because there is no isolation requirement, the SR gate driving becomes so simple that the voltage at the complementary controlled bridge can be used to directly drive the SR gate. Both the gate driving loss and the SR body diode conduction loss are reduced. The proposed circuit achieves similar overall efficiency to a conventional 300kHz buck converter running at 1MHz. All the circuits proposed in this dissertation can use coupling inductors to improve both the steady-state efficiency and dynamic performances. The essence of the coupling inductors concept is to provide different equivalent inductances for the steady state and the transient. Moreover, when a current loop becomes necessary to achieve proper current sharing among phases, the current loop sample hold effect will make it difficult to push the bandwidth. The sample hold effect is alleviated by the coupling inductors concept. A small-signal model is proposed to study the system dynamic performance difference with different coupling inductor designs. As the verification, the coupling concept is applied to the 12V non-isolated CCB self-driven VRM and the bandwidth as high as one third of the switching frequency is achieved, which means a significant output capacitor reduction. / Ph. D.

The use of computers in the modern world has become prevalent in all aspects of life. The size of these machines has decreased dramatically while the capability has increased exponentially. A special DC-DC converter called a VRM (Voltage Regulator Module) is used to power these machines. The VRM faces the task of supplying high current and high di/dt to the microprocessor while maintaining a tight load regulation. As computers have advanced, so have the VRM's used to power them. Increasing the current and di/dt of the VRM to keep up with the increasing demands of the microprocessor does not come without a cost. To provide the increased di/dt, the VRM must use a higher number of capacitors to supply the transient energy. This is an undesirable solution because of the increased cost and real estate demands this would lead to in the future. Another solution to this problem is to increase the switching frequency and control bandwidth of the VRM. As the switching frequency increases the VRM is faced with efficiency and thermal problems. The current buck topologies suffer large drops in efficiency as the frequency increases from high switching losses. Resonant or soft switching topologies can provide a relief from the high switching loss for high frequency power conversion. One disadvantage of the resonant schemes is the increased conduction losses produced by the circulating energy required to produce soft switching. As the frequency rises, the additional conduction loss in the resonant schemes can be smaller than the switching loss encountered in the hard switched buck. The topology studied in this work is the 12V non-isolated ZVS self-driven presented in [1]. This scheme offered an increased efficiency over the state of the art industry design and also increased the switching frequency for capacitor reduction. The goal of this research was to study this topology and improve the magnetic design to decrease the cost while maintaining the superior performance. The magnetics used in resonant converters are very important to the success of the design. Often, the leakage inductance of the magnetics is used to control the ZVS or ZCS switching operation. This work presents a new improved magnetic solution for use in the 12V non-isolated ZVS self-driven scheme which increases circuit operation, flexibility, and production feasibility. The improved magnetic structure is simulated using 3D FEA verification and verified in hardware design. / Master of Science

With fast development of semiconductor industry, the transistors in microprocessors increase dramatically, which follows the Moore’s law. As a result, the operating voltages of the future microprocessors follow the trend of decreasing (sub 1V) while the demanding currents increase (higher than 100A). Furthermore, the high slew rates during the transient will reach 1200 A/us. All these impose a serious challenge on a Voltage Regulator (VR) or Voltage Regulator Module (VRM). In order to meet requirements of the next generation microprocessors, four new ideas are proposed in this thesis. The first contribution is an accurate analytical loss model of a power MOSFET with a Current-Source Driver (CSD). The impact of the parasitic components is investigated. Based on the proposed loss model, a general method to optimize the CSD is presented. With the proposed optimization method, the CSD improves the efficiency from 79.4% using the conventional voltage source driver to 83.6% at 12V input, 1.5V/30A output and 1MHz. The second contribution is a new continuous CSD for a synchronous buck converter. The proposed CSD is able to drive the control and Synchronous Rectifier (SR) MOSFETs independently with different drive currents enabling optimal design. At 12V input, 1.5 V/30A output and 1MHz, the proposed CSD improves the efficiency from 79.4% using a conventional voltage source driver to 83.9%. The third contribution is a new discontinuous CSD. The most important advantage of the new CSD is the small inductance (typically, 20nH at 1MHz switching frequency). A hybrid gate drive scheme for a synchronous buck converter is also proposed. The idea of the hybrid gate driver scheme is to use the CSD to achieve switching loss reduction for the control MOSFET, while use the conventional voltage source driver for the SR. At 12V input, 1.3V/25A output and 1MHz, the proposed CSD improves the efficiency from 80.7% using the voltage source driver to 85.4%. The final contribution is new self-driven zero-voltage-switching (ZVS) non-isolated full-bridge converters for 12V input VRM applications. The proposed converter achieves the duty cycle extension, ZVS operation and SRs gate energy recovery. At 12V input, 1.3V output and 1MHz, the proposed converter improves the efficiency from 80.7% using the buck converter to 83.6% at 50A. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-23 08:59:12.699

With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements, but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. Recently, data centers have replaced the 12V DC server rack distribution with a 48V DC distribution, producing a significant overall system efficiency improvement. However, 48V rack architecture raises significant challenges for the voltage regulator modules (VRMs) required for powering the processor. The 48V VRM in the vicinity of the CPU needs to be designed with very high efficiency, high power density, high light-load efficiency, as well as meet all transient requirements by the CPU and GPU. Transferring the well-developed multi-phase buck converter used in the 12V VRM to the 48V distribution platform is not that simple. The buck converter operating with 48V, stepping down to sub 2V, will be subjected to significant switching related loss, resulting in lower overall system efficiency. These challenges drive the need to look for more efficient architectures for 48V VRM solutions. Two-stage conversions can help solve the design challenges for 48V VRMs. A first-stage unregulated converter is used to step-down the 48V to a specific intermediate bus voltage. This voltage will feed a multi-phase buck converter that powers the CPU. An unregulated LLC converter is used for the first-stage converter, with zero voltage switching (ZVS) operation for the primary side switches, and zero current switching (ZCS) along with ZVS operation, for the secondary side synchronous rectifiers (SRs). The LLC converter can operate at high frequency, in order to reduce the magnetic components size, while achieving high-efficiency. The high-efficiency first-stage, along with the scalability and high bandwidth control of the second-stage, allows this architecture to achieve high-efficiency and power density. This architecture is simpler to adopt by industry, by plugging the unregulated converter before the existing multi-phase buck converters on today's platforms. The first challenge for this architecture is the transformer design of the first-stage LLC converter. It must avoid all of the loss associated with high frequency operations, and still achieve high power density without scarifying efficiency. In this thesis, the integrated matrix transformer structure is optimized by SR integration with windings, interleaved primary side termination, and a better PCB winding arrangement to achieve high-efficiency and power density, and minimize the losses associated with high-frequency operations. The second challenge is the light load efficiency improvement. In this thesis a light load efficiency improvement is proposed by a dynamic change of the intermediate bus voltage, resulting in more than 8 % light load efficiency improvements. The third challenge is the selection of the optimal bus voltage for the two-stage architecture. The impact of different bus voltages was analyzed in order to maximize the overall conversion efficiency. Multiple 48V unregulated converters were designed with maximum efficiency >98 %, and power densities >1000 W/in3, with different output voltages, to select the optimal bus voltage for the two-stage VRM. Although the two-stage VRM is more scalable and simpler to design and adopt by current industry, the efficiency will reduce as full power flows in two cascaded DC/DC converters. Single-stage conversion can achieve higher-efficiency and power-density. In this thesis, a quasi-parallel Sigma converter is proposed for the 48V VRM application. In this structure, the power is shared between two converters, resulting in higher conversion efficiency. With the aid of an optimized integrated magnetic design, a Sigma converter suitable for narrow voltage range applications was designed with 420 W/in3 and a maximum efficiency of 94 %. Later, another Sigma converter suitable for wide voltage range applications was designed with 700W/in3 and a maximum efficiency of 95 %. Both designs can achieve higher efficiency than the two-stage VRM and all other state-of-art solutions. The challenges associated with the Sigma converter, such as startup and closed loop control were addressed, in order to make it a viable solution for the VRM application. The 48V rack architecture requires regulated 12V output converters for various loads. In this thesis, a regulated LLC is used to design a high-efficiency and power-density 48V bus converter. A novel integration method of the inductor and transformer helps the LLC achieve the required regulation capability with minimum losses, resulting in a converter that can provide 1KW of continuous power with efficiency of 97.8 % and 700 W/in3 power density. This dissertation discusses new power architectures with an optimized design for the 48V rack architectures. With the academic contributions in this dissertation, different conversion architectures can be utilized for 48V VRM solutions that solve all of the challenges associated with it, such as scalability, high-efficiency, high density, and high BW control. / Doctor of Philosophy / With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. The data center manufacturers have recently adopted a more efficient architecture that supplies a 48V DC server rack distribution instead of a 12V DC distribution to the server motherboard. This helped reduce costs and losses, but as a consequence, raised a challenge in the design of the DC/DC voltage regulator modules (VRM) supplied by the 48V, in order to power the CPU and GPU. In this work, different architectures will be explored for the 48V VRM, and the trade-off between them will be evaluated. The main target is to design the VRM with very high-efficiency and high-power density to reduce the cost and size of the CPU/GPU motherboards. First, a two-stage power conversion structure will be used. The benefit of this structure is that it relies on existing technology using the 12V VRM for powering the CPU. The only modification required is the addition of another converter to step the 48V to the 12V level. This architecture can be easily adopted by industry, with only small modifications required on the system design level. Secondly, a single-stage power conversion structure is proposed that achieves higher efficiency and power density compared to the two-stage approach; however, the structure is very challenging to design and to meet all requirements by the CPU/GPU applications. All of these challenges will be addressed and solved in this work. The proposed architectures will be designed using an optimized magnetic structure. These structures achieve very high efficiency and power density in their designed architectures, compared to state-of-art solutions. In addition, they can be easily manufactured using automated manufacturing processes.

The emergence of the Intel Pentium TM processor necessitates that a dedicated converter, the voltage regulator module (VRM), be physically located very close to the processor in computer power systems. The efficiency and transient response specifications of the VRM place contradictory requirements on the inductance. This dissertation discusses possible VRM inductor designs to improve efficiency without compromising transient responses. The multi-channel interleaving buck converter is the most popular topology for present VRMs. Analysis in this work shows that the small-signal model of an n-channel interleaving buck can be simplified as a single buck converter. The equivalent inductance is 1/n of the inductance in the interleaving channel. The equivalent switching frequency is n times the switching frequency in each channel. Through the transient response analysis, the critical inductance of the VRM is identified. The critical inductance is a tradeoff point between transient response and efficiency. The inductances smaller than the critical inductance have equal transient responses. For the inductances larger than the critical inductance, the VRM transient voltage spikes increase with the inductance. The critical inductance is the largest inductance that gives the fastest transient responses. The critical inductance is a function of the control bandwidth and the load transient steps. Although multi-channel interleaving reduces the current ripple stress on the output capacitors, it cannot reduce the current ripples in each channel. The large current ripples reduce the efficiency of the VRM. With the proposed concept of integrated coupling inductors between channels, the converters have larger equivalent inductances in steady-state operation and smaller equivalent inductances in transient response. The steady-state current ripples can be reduced without compromising the transient response. The overall efficiency of the converter is improved. In order to evaluate the application of the coupling inductor concept in multi-channels, an appropriate magnetic model is required. This dissertation proposes a flux reluctance model for the core and winding structures. With this reluctance model and mathematical transformations, the coupled inductors can be decoupled in the electric circuit simulation model. This reduces the complexity of the model when a large number of inductors are coupled. The model can be easily scaled to model the structures that involve more inductors. Examples are presented to show the application of this proposed model. / Ph. D.

This thesis presents a novel Resonant Switched-Capacitor Converter with Multiple Resonant Frequencies, abbreviated as MRSCC for both high density and efficiency non-isolated large step-down Intermediate Bus Converter (IBC). Conventional Resonant Switched-Capacitor Converter (RSCC) proposed by Shoyama and its high voltage conversion ratio derivation such as Switched-Tank Converter (STC) by Jiang and li employ half sinusoidal-current charge transfer method between capacitors to achieve high efficiency and density operation by adding a small resonant inductor in series to pure switched-capacitor converter's (SCC) flying capacitor. By operating switching frequency to be the same as its resonant frequency, RSCC achieves zero-current turn off operation, however, this cause RSCC and its derivation suffer from component variation issue for high-volume adoption. Derived from RSCC, MRSCC adds additional high frequency resonant component, operates only during its dead-time, by adding small capacitor in parallel to RSCC's resonant inductor. By operating switching frequency higher than its main resonant frequency, MRSCC utilizes double chopped half-sinusoidal current charge transfer method between capacitors to further improve efficiency. In addition, operating switching frequency consistently higher than its resonant frequency, MRSCC provides high immunity towards component variation, making it and its derivation viable for high-volume adoption. / MS / Following the recent trend, most internet services are moving towards cloud computing. Large data applications and growing popularity of cloud computing require hyperscale data centers and it will continue to grow rapidly in the next few years to keep up with the demand [4]. These cutting-edge data centers will require higher performance multi-core CPU and GPU installations which translates to higher power consumption. From 10MWatts of power, typical data centers deliver only half of this power to the computing load which includes processors, memory and drives. Unfortunately, the rest goes to losses in power conversion, distribution and cooling [5]. Industry members look into increasing backplane voltage from 12V to 48V in order to reduce distribution loss. This thesis proposes a novel Resonant Switched-Capacitor Converter using Multiple Resonant Frequencies to accommodate this increase of backplane voltage.

L’apparition de convertisseurs multicellulaires parallèles entrelacés et magnétiquement couplés a conduit ces dernières années à améliorer les performances des convertisseurs (densité de puissance, efficacité, dynamique,...). Il existe plusieurs topologies d’entrelacement qui utilisent des Transformateurs Interphases. L’objectif principal de cette étude est de trouver parmi ces topologies celles qui sont les mieux adaptées à un contexte d’intégration d’électronique de puissance pour minimiser la taille et réduire les pertes. Une première étape de modélisation a permis d’effectuer une étude comparative de quelques topologies. Un procédé de permutation des phases d’alimentation a été présenté afin de réduire les ondulations du courant de phases et les pertes ohmiques. Les résultats obtenus valident qualitativement l’avantage de la solution retenue par rapport à la solution standard. Enfin, la réalisation pratique d’un prototype de convertisseur modulaire utilisant des Transformateurs Inter-phases est abordé. Il s’agit d’un régulateur chargé d’alimenter les microprocesseurs (1,2V/100A) (Voltage Regulator Module (VRM)) à 5 modules. Les résultats expérimentaux montrent l’avantage de l’utilisation des Transformateurs Inter-phases par rapport à la solution classique / During the last years, using coupled parallel interleaved converters enhances converters performances (power density, efficiency, transient response,...). There are several possible interleaved coupled topologies that use Inter-phases Transformers. The main objective of this study is to find among these topologies the best adapted configuration in a context of power electronics integration in order to minimize converter size and to reduce losses. A model is proposed to compare some topologies. An optimal modified sequence of phase order to reduce current ripple and ohmic losses is presented. The obtained results validate the advantage of the coupled solution compared to the standard solution. At last, the implementation of a modular power converter using Inter-phases Transformers is shown. It is a Voltage Regulator Module (1,2V/100A) that consists of five identical modules. Experimental results show the advantage of using Inter-phases Transformers compared to conventional solution