With lower output voltage (lower than 1V) and higher output current (more than 160A) required in the near future, the voltage regulators for the microprocessors, a kind of special power supplies are facing more and more critical challenges to achieve high efficiency and high power density. 90% plus efficiency for CPU VRs is expected from industry not only for the thermal management, but also for saving on electricity costs, especially for the large data-center systems. At the same time, high power density VRs are also desired due to the increasing power consumption of microprocessors as well as the precious space on CPU motherboard. Current multi-phase Buck VR has its limitation to achieve 90% plus efficiency. With the state of art devices, the single-stage 12V/1.2V 600kHz Buck VR achieves 85% to 86% efficiency at full load condition. In addition, for the future lower output voltage application, the Buck efficiency will drop another 3~4% due to the extreme small duty cycle. From the power density point of view, due to the switching frequency limitation (normally, from 300 kHz to 600 kHz for typical CPU VRs) for acceptable efficiency performance, the multi-phase Buck VR is unable to ensure a small size since it needs bulky output capacitors to meet the challenging transient requirement as well as the output impedance requirement with relatively low bandwidth design. To attain high efficiency and high power density at the same time, in-series two-stage power architecture was proposed. By cutting the single stage into two and utilizing the low voltage devices, the in-series two stages can achieve around 87% efficiency which is similar as single stage with second-stage operating at 1 MHz for less cost. Compared with the in-series one, the other two-stage power architecture is called "Sigma" architecture which is composed by an unregulated converter (DCX) and a regulated buck converter, with a special connection where the inputs are in series while outputs are paralleled. Through this topology, unlike the in-series two-stage where both two stages deliver the full load power, the power will be distributed between unregulated DCX and regulated Buck. If the unregulated DCX can achieve high efficiency, let most power be handled by it and just small power from buck, the Sigma architecture can achieve high efficiency performance based on this concept. The design consideration and process had been investigated by CPES previous graduates. By the designed 1.2V/120A Sigma VR circuit, approaching 90% efficiency was achieved which is around 3~4% efficiency higher than state of the art multi-phase Buck VR. However, it is not the optimal design for best efficiency performance, the improvement methods for higher efficiency is deeply considered and the efficiency potential benefit of this special structure will be clarified in this thesis. Besides the efficiency interest, transient performance of Sigma VR is also a challenging issue needed to be addressed. The state of the art Buck VR needs a bunch of output bulk capacitors to meet the stringent output impedance requirement from Intel and those output bulk capacitors occupy too much space in the motherboard. For Sigma architecture, through the help of the low impedance DCX which can achieve faster current dynamic response, some low voltage bulk capacitors could be replaced by smaller input high voltage capacitors. It is still not clear for us to identify how input capacitor impacts the DCX dynamic current response and how to best choose this impact factor. This thesis will investigate the faster DCX dynamic current performance of Sigma VR, and explain the dynamic impacts from input capacitors, from control design and from DCX impedance Lout. The high voltage capacitors could provide energy through low impedance DCX to deal with the transient load with smaller capacitance, resulting less total cost and footprint with conventional Buck solution. Low impedance DCX is also a desire for achieving fast current response for providing a "non-obstacle" path when energy transferring from input capacitors. The control also has the impact to the DCX current response when the bandwidth is higher than certain frequency. The transient benefit will also be discussed from impedance perspective. In order to improve the efficiency and power density of Sigma VR, several methods are proposed. As a critical component of DCX, the transformer design determines the performance of Sigma VR both to efficiency and power density. By optimizing the transformer design to achieve lower winding loss and smaller leakage inductance, the higher efficiency and faster transient DCX can be obtained. Changing the output capacitors to ceramic ones is helpful when control bandwidth is greater than 100 kHz for both lower cost and smaller footprint. Continually pushing bandwidth can reduce the required output ceramic capacitor number further. In addition, from the study of the loss breakdown, by adjusting the energy ratio of DCX and Buck can achieve higher efficiency based on current device level. What is more, with the same simple concept of adjusting power ratio of DCX and Buck, with the development of devices in the future as well as higher efficiency DCX, Sigma architecture will be more attractive for future's lower output voltage VR application. And it will also be more efficient considering higher than 12V input bus voltage by letting high efficiency DCX handle more power. Utilizing this characteristic, changing the power system delivery architecture from AC input to the microprocessors, the end to end efficiency could be improved. / Master of Science

Since the early 80s, the computer industry has undergone great expansion. Processors are becoming faster and more powerful. Power management issues in computing systems are becoming more and more complex and challenging. An evolution began when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. A so-called Voltage Regulator Module (VRM) is put close to the processor in order to provide the power as quickly as possible. Nowadays, for desktop and workstation applications, VRM input voltage has moved to the 12V output of the silver box. In the meantime, microprocessors will run at very low voltage (below 1V), will consume up to 100A of current, and will have dynamics of about 400A/us. In the near future, VRM will be replaced with VRD because of the parasitic components effect. The specifications requirements for VRD are even more challenging than VRM. With this kind of tight tolerance, high current and fast current slew rate, transient response requirements for VRD design are very challenging, especially for step-down transient. During step-down transient, there is some additional energy stored in inductor. Traditional switching regulator like multi-phase buck can do nothing for this even by saturating the duty cycle to 0. All of the additional energy in inductor will be dumped into output cap and cause a large voltage spike at the output voltage. Even for step-up transient, traditional linear control like voltage loop control can't provide enough bandwidth because of the slow compensation and slow slew rate of the error amplifier. So the voltage drop is still quite large. Comparing with traditional linear controlled switching regulator such as voltage control and current control buck converter, active clamp has a lot of the advantages for the transient response. With proper design, active clamp can generate a very high bandwidth since there is no compensator needed in the control loop. Since active clamp bypasses inductor and is connected directly to the output cap, it can quickly source and sink current from the output cap even during the step-down transient and prevent overshooting of the output voltage. This is the biggest advantage for active clamp comparing with traditional linear control. In this thesis, a new active clamp structure is proposed. Several new concepts are proposed like non-linear Gm, built-in offset Gm, error signal feedback and AVP design. A one-channel buck converter with new active clamp and voltage loop control is implemented and verified using real transistors based on 0.5um CMOS process. / Master of Science

The use of computers in the modern world has become prevalent in all aspects of life. The size of these machines has decreased dramatically while the capability has increased exponentially. A special DC-DC converter called a VRM (Voltage Regulator Module) is used to power these machines. The VRM faces the task of supplying high current and high di/dt to the microprocessor while maintaining a tight load regulation. As computers have advanced, so have the VRM's used to power them. Increasing the current and di/dt of the VRM to keep up with the increasing demands of the microprocessor does not come without a cost. To provide the increased di/dt, the VRM must use a higher number of capacitors to supply the transient energy. This is an undesirable solution because of the increased cost and real estate demands this would lead to in the future. Another solution to this problem is to increase the switching frequency and control bandwidth of the VRM. As the switching frequency increases the VRM is faced with efficiency and thermal problems. The current buck topologies suffer large drops in efficiency as the frequency increases from high switching losses. Resonant or soft switching topologies can provide a relief from the high switching loss for high frequency power conversion. One disadvantage of the resonant schemes is the increased conduction losses produced by the circulating energy required to produce soft switching. As the frequency rises, the additional conduction loss in the resonant schemes can be smaller than the switching loss encountered in the hard switched buck. The topology studied in this work is the 12V non-isolated ZVS self-driven presented in [1]. This scheme offered an increased efficiency over the state of the art industry design and also increased the switching frequency for capacitor reduction. The goal of this research was to study this topology and improve the magnetic design to decrease the cost while maintaining the superior performance. The magnetics used in resonant converters are very important to the success of the design. Often, the leakage inductance of the magnetics is used to control the ZVS or ZCS switching operation. This work presents a new improved magnetic solution for use in the 12V non-isolated ZVS self-driven scheme which increases circuit operation, flexibility, and production feasibility. The improved magnetic structure is simulated using 3D FEA verification and verified in hardware design. / Master of Science

This master’s thesis deals with the design of integrated voltage regulator. Topologies of linear voltage regulators and their stability are discussed. Part of the thesis deals with description and simulation of blocks of selected regulator topology. The thesis describes the difficulties of integrated circuit design in the automotive industry. The electrical scheme of the designed regulator is explained. The work also focuses on the stability of designed regulator. Then presents simulations. It discusses the layout of integrated circuits and the designed voltage regulator.

Thesis (MScEng (Electrical and Electronic Engineering))--Stellenbosch University, 2008. / ENGLISH ABSTRACT: This thesis discusses the development of a 5 kVA single phase AC voltage regulator, specifically designed to assist in the reduction of electrification costs in sparsely populated rural areas. The voltage regulator is based on a solid state auto-transformer tap changer, designed to be robust and maintenance free. Electrification cost savings can be realized if the length of the LV network can be extended to reach more households. To accomplish this, a voltage regulator can be installed onto the extended LV feeder at the point where the LV voltage will drop below the minimum valid voltage, thereby boosting the voltage downstream and enabling more customers to be connected. A variety of voltage regulator topologies were investigated to obtain the best topology for the application. The voltage regulator design is discussed in detail with careful attention given to the power loss incurred, surge voltage protection requirements, protection coordination with the existing LV network and the thermal design requirements. An electronic controller based on a digital signal processor together with an appropriate power supply is designed and built. The software to control the voltage regulator is developed, integrated with the hardware and debugged. The complete voltage regulator is evaluated through extensive laboratory testing and field trials are performed to verify the performance of the device. / AFRIKAANSE OPSOMMING: Hierdie tesis bespreek die ontwikkeling van ‘n 5 kVA, enkelfase, wisselstroom spannings reguleerder, spesifiek ontwerp om koste besparings te bewerkstellig in die elektrifisiëring van yl bevolkte landelike gemeenskappe. Die spannings reguleerder se ontwerp is gebaseer op ‘n outo-transformator tap wisselaar met vaste toestand skakelaars, om sodoende robuust en instandhoudings vry te funksioneer. Elektrifisiërings koste besparings is moontlik indien die laag spannings distribusie kabel verleng kan word, om sodoende elektrisiteit aan meer huishoudings te voorsien. Om dit mootlik te maak kan ‘n spannings reguleerder geinstalleer word op die punt waar die kabel spanning onder die minimum toegelate spanning daal. Sodoende word die spanning weer verhoog aan al die huishoudings wat aan die verlengde gedeelte van die kabel verbind is. ‘n Verskeidenheid uiteenlopende spannings reguleerder topologieë is ondersoek om die beste topologie vir die toepassing te identifiseer. Die ontwerp van die spannings reguleerder is baie deeglik bespreek en spesifieke aandag is gegee aan die verliese, spits opwelling spannings beveiliging, sinkronisasie met die huidige laag spannings netwerk se beveiligings meganismes en die termiese ontwerp van die stelsel. ‘n Elektroniese beheerder, gebaseer op ‘n digitale sein verwerker, tesame met ‘n toepaslike kragbron is ontwerp en gebou. Die nodige sagteware om die spannings reguleerder te beheer is ontwikkel, geintegreer met die hardeware en ontfout. Die volledige spannings reguleerder is ontleed deur intensiewe toetse in die laboratorium en toets installasies op laag spannings netwerke, om sodoende die nakoming van die werks verrigting vereistes van die toestel te bevestig.

Distributed on-chip voltage regulation where multiple voltage regulators are distributed among different locations of the chip demonstrates advantages as compared to on-chip voltage regulation utilizing a single voltage regulator. Better on-chip voltage noise performance and faster transient response can be realized due to localized voltage regulation. Despite the advantages of distributed on-chip voltage regulation, unbalanced current sharing issue can occur among each voltage regulator, which has been demonstrated to deteriorate power conversion efficiency, stability, and reliability of the power delivery network. An effective balanced current sharing scheme that can be applied to most voltage regulator types is proposed to balance the current sharing. Furthermore, a relatively high on-chip temperature induced by increased power density leads to prominent voltage regulator performance degradations due to aging. The emerging type of digital low-dropout regulator is investigated regarding aging induced transient and steady state performance degradations. Reliability enhancement techniques for digital low-dropout regulators are developed and verified. Such techniques introduce negligible power and area overhead and do not affect the normal operations of digital low-dropout regulators. Reliability enhancement techniques also reduce the area overhead needed to mitigate aging induced performance degradations. Area overhead saving further translates into more space for increased number of distributed on-chip voltage regulators, enabling scalable on-chip voltage regulation.

<p>Many analog systems need a stable power supply voltage that does not vary with temperature and time in order to operate properly. In a battery operated system the battery voltage is not stable, e.g. it decreases with decreasing temperature and with ageing. In that case a voltage regulator must be used, that regulates the battery voltage and generates a stable supply voltage to power other circuitry. </p><p>In this thesis a voltage regulator to be used in a battery operated system has been designed which meets the given specification of stability and power capabilities. A voltage reference, which is a commonly used devise in analog circuits, was also designed. The role of a reference voltage in an electrical system is the same as for a tuning fork in a musical ensemble; to set a standard to which other voltages are compared. </p><p>A functionality to detect when the lifetime of the battery is about to run out was also developed.</p>

The sale of hybrid electric vehicles (HEVs) has increased tenfold from the year 2001 to 2009 [1]. With this the demand for high temperature electronics has also increased dramatically making, high temperature electronics for HEV applications desirable in the engine compartment, power train, and brakes where the ambient temperature normally exceeds 150°C. Power converters (i.e. DC-DC converter, DC-AC inverter) inside the HEVs require gate drivers to control the power switches. An integrated gate driver circuit has been realized in 0.8-um BCD-on-SOI process. This gate driver IC needs a step-down voltage regulator to convert the unregulated high input DC voltage (VDDH) to a regulated nominal CMOS voltage (i.e. 5 V). This step-down voltage regulator will supply voltage to the low-side buffer (pre-driver) and other digital and analog circuits inside the gate driver ICs. A linear voltage regulator is employed to accomplish this task; however, very few publications on high temperature voltage regulators are available. This research presents a high temperature linear voltage regulator designed and fabricated in a commercially available 0.8-um BCD-on-SOI process. SOI processes typically offer reduced junction leakage current by three orders of magnitude compared to the bulk-CMOS processes at temperatures beyond 150°C. In addition, a pole swap compensation technique is utilized to achieve stability over a wide range (four decades) of load current. The error amplifier inside the regulator is designed using an inversion coefficient based design methodology, and a temperature stable current reference is used to bias the error amplifier. The linear regulator provides an output voltage of 5.3 V at room temperature and can supply a maximum load current of 200 mA.

Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator was developed to meet the demands of a gate driver IC. The voltage regulator must provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −50 ºC to 200 ºC, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation and thus lower operating junction temperature. This regulator is based on the LM723 Zener reference voltage regulator which allows stable performance over temperature (provided proper design of the temperature compensation scheme). This circuit topology and the SOI silicon process allow for reliable operation under all application demands. The designed voltage regulator has been successfully tested from −50 ºC to 200 ºC while demonstrating an output voltage variation of less than 25 mV under the full range of input voltage. Line regulation tests from 10 V to 35 V show a 3.7-ppm/V supply sensitivity. With the use of a high-temperature ceramic output capacitor, a 5-nsec edge, 0 to 220 mA, 1-µsec pulse width load current induced only a 55 mV drop in regulator output voltage. In the targeted application, load current pulse widths will be much shorter, thereby improving the load transient performance. Full temperature and input voltage range tests reveal the no-load supply current draw is within 330 µA while still providing an excess of 200 mA of load current upon demand.

This thesis work describes the implementation perspective of an integrated high efficiency DC-DC converter implemented in 65 nm CMOS. The implemented system employs the Buck converter topology to down-convert the input battery voltages. This converter offers its use as a power management unit in portable battery operated devices. This thesis work includes the description of a basic Buck converter along with the various key equations involved which describe the Buck operation as well as are used to deduce the requirements for the various internal building blocks of the system. A detailed description of the operation as well as the design of each of the building blocks is included. The implemented system can convert the input battery voltage in the range of 2.3 V to 3.6 V into an output supply voltage of 1.6 V. The system uses dual-mode feedback control to maintain the output voltage at 1.6 V. For the low load currents the PFM feedback control is used and for the higher load currents the PWM feedback control is used. This converter can supply load currents from 0 to 300 mA with efficiency above 85%. The static line regulation of the system is &lt; 0.1% and the load regulation of the system is &lt; 0.3%. A digital soft-start circuit is implemented in this system. The system also includes the capability to trim the output voltage in ~14 mV steps depending on the 4-bit input digital code.