Many analog systems need a stable power supply voltage that does not vary with temperature and time in order to operate properly. In a battery operated system the battery voltage is not stable, e.g. it decreases with decreasing temperature and with ageing. In that case a voltage regulator must be used, that regulates the battery voltage and generates a stable supply voltage to power other circuitry. In this thesis a voltage regulator to be used in a battery operated system has been designed which meets the given specification of stability and power capabilities. A voltage reference, which is a commonly used devise in analog circuits, was also designed. The role of a reference voltage in an electrical system is the same as for a tuning fork in a musical ensemble; to set a standard to which other voltages are compared. A functionality to detect when the lifetime of the battery is about to run out was also developed.

With increasing level of distributed generation¡]DG¡^on radial feeders in electric distribution systems, it could cause over-voltages as well as under-voltages depending on several factors including DG capacity, locations, and the strategy of voltage regulation. This thesis describes the typical and proposed voltage control strategies that could allow the increase of DG interconnection capacity. By using probabilistic load flow technique, voltage regulation performance for cases with different levels of DG outputs, demands and voltage control strategies are presented. They are compared by using a voltage profile improvement index and a risk assessment technique.

Developments in automotive (particularly hybrid electric vehicles), aerospace, and energy production industries over the recent years have led to expanding research interest in integrated circuit (IC) design toward high-temperature applications. A high-voltage, high-temperature SOI process allows for circuit design to expand into these extreme environment applications. Nearly all electronic devices require a reliable supply voltage capable of operating under various input voltages and load currents. These input voltages and load currents can be either DC or time-varying signals. In this work, a stable supply voltage for embedded circuit functions is generated on chip via a voltage regulator circuit producing a stable 5-V output voltage. Although applications of this voltage regulator are not limited to gate driver circuits, this regulator was developed to meet the demands of a gate driver IC. The voltage regulator must provide reliable output voltage over an input range from 10 V to 30 V, a temperature range of −50 ºC to 200 ºC, and output loads from 0 mA to 200 mA. Additionally, low power stand-by operation is provided to help reduce heat generation and thus lower operating junction temperature. This regulator is based on the LM723 Zener reference voltage regulator which allows stable performance over temperature (provided proper design of the temperature compensation scheme). This circuit topology and the SOI silicon process allow for reliable operation under all application demands. The designed voltage regulator has been successfully tested from −50 ºC to 200 ºC while demonstrating an output voltage variation of less than 25 mV under the full range of input voltage. Line regulation tests from 10 V to 35 V show a 3.7-ppm/V supply sensitivity. With the use of a high-temperature ceramic output capacitor, a 5-nsec edge, 0 to 220 mA, 1-µsec pulse width load current induced only a 55 mV drop in regulator output voltage. In the targeted application, load current pulse widths will be much shorter, thereby improving the load transient performance. Full temperature and input voltage range tests reveal the no-load supply current draw is within 330 µA while still providing an excess of 200 mA of load current upon demand.

With fast development of semiconductor industry, the transistors in microprocessors increase dramatically, which follows the Moore’s law. As a result, the operating voltages of the future microprocessors follow the trend of decreasing (sub 1V) while the demanding currents increase (higher than 100A). Furthermore, the high slew rates during the transient will reach 1200 A/us. All these impose a serious challenge on a Voltage Regulator (VR) or Voltage Regulator Module (VRM). In order to meet requirements of the next generation microprocessors, four new ideas are proposed in this thesis. The first contribution is an accurate analytical loss model of a power MOSFET with a Current-Source Driver (CSD). The impact of the parasitic components is investigated. Based on the proposed loss model, a general method to optimize the CSD is presented. With the proposed optimization method, the CSD improves the efficiency from 79.4% using the conventional voltage source driver to 83.6% at 12V input, 1.5V/30A output and 1MHz. The second contribution is a new continuous CSD for a synchronous buck converter. The proposed CSD is able to drive the control and Synchronous Rectifier (SR) MOSFETs independently with different drive currents enabling optimal design. At 12V input, 1.5 V/30A output and 1MHz, the proposed CSD improves the efficiency from 79.4% using a conventional voltage source driver to 83.9%. The third contribution is a new discontinuous CSD. The most important advantage of the new CSD is the small inductance (typically, 20nH at 1MHz switching frequency). A hybrid gate drive scheme for a synchronous buck converter is also proposed. The idea of the hybrid gate driver scheme is to use the CSD to achieve switching loss reduction for the control MOSFET, while use the conventional voltage source driver for the SR. At 12V input, 1.3V/25A output and 1MHz, the proposed CSD improves the efficiency from 80.7% using the voltage source driver to 85.4%. The final contribution is new self-driven zero-voltage-switching (ZVS) non-isolated full-bridge converters for 12V input VRM applications. The proposed converter achieves the duty cycle extension, ZVS operation and SRs gate energy recovery. At 12V input, 1.3V output and 1MHz, the proposed converter improves the efficiency from 80.7% using the buck converter to 83.6% at 50A. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-04-23 08:59:12.699

abstract: Power management plays a very important role in the current electronics industry. Battery powered and handheld applications require novel power management techniques to extend the battery life. Most systems have multiple voltage regulators to provide power sources to the different circuit blocks and/or sub-systems. Some of these voltage regulators are low dropout regulators (LDOs) which typically require output capacitors in the range of 1's to 10's of µF. The necessity of output capacitors occupies valuable board space and can add additional integrated circuit (IC) pin count. A high IC pin count can restrict LDOs for system-on-chip (SoC) solutions. The presented research gives the user an option with regard to the external capacitor; the output capacitor can range from 0 - 1µF for a stable response. In general, the larger the output capacitor, the better the transient response. Because the output capacitor requirement is such a wide range, the LDO presented here is ideal for any application, whether it be for a SoC solution or stand-alone LDO that desires a filtering capacitor for optimal transient performance. The LDO architecture and compensation scheme provide a stable output response from 1mA to 200mA with output capacitors in the range of 0 - 1µF. A 2.5V, 200mA any-cap LDO was fabricated in a proprietary 1.5µm BiCMOS process, consuming 200µA of ground pin current (at 1mA load) with a dropout voltage of 250mV. Experimental results show that the proposed any-cap LDO exceeds transient performance and output capacitor requirements compared to previously published work. The architecture also has excellent line and load regulation and less sensitive to process variation. Therefore, the presented any-cap LDO is ideal for any application with a maximum supply rail of 5V. / Dissertation/Thesis / M.S. Electrical Engineering 2012

FundaÃÃo Cearense de Apoio ao Desenvolvimento Cientifico e TecnolÃgico / This work aims to quantify the impact in the steady state operation of a distribution system when electric vehicles are connected. It is worth noting that the connection of them may cause significant changes in the voltage profile, in the degree of voltage unbalance and in the electrical losses of the system. In order to make this analysis, a three-phase power flow program was developed in MATLAB language. This program is based on the Ladder Iterative Technique and it contains models of overhead distribution lines, underground distribution lines, spot loads, distributed loads connected in wye and delta, step voltage regulators, capacitor banks, three-phase transformers and the model of an electric vehicle. This model allows simulation of a real electric vehicle of model Tesla Roadster, produced by Tesla Motors. The test system used in all simulations was the IEEE 13 bus. Moreover, the methodology consisted in simulate the system with the voltage regulator and without the voltage regulator under heavy load and light load conditions. The electric vehicle was connected to a specific systemâs bus and it were considered that it could work as a load or as a distributed generator with or without positive sequence voltage control. Constants configurations of the electric vehicles were considered for the heavy load and light load cases. The results of the simulations reveal there was voltage violation due to the connection of electric vehicles acting as loads in the test system under heavy load conditions without voltage regulator. When they operate as generators, they can maintain the voltage unbalance under the allowed 2%, turning the systemâs voltages more balanced. There were significant reductions when the electric vehicles acted as a load (71.1%) and as generator (77.5%) on the total real power losses when the system operated with voltage regulator on the substation and the electric vehicles operated with positive sequence voltage control (specified at 1,0 pu). / Este trabalho tem o objetivo de quantificar o impacto da conexÃo de veÃculos elÃtricos na operaÃÃo em regime permanente de um sistema de distribuiÃÃo. à visto que a conexÃo dos mesmos pode causar mudanÃas significativas no perfil de tensÃes, no grau de desequilÃbrio de tensÃo e nas perdas elÃtricas do sistema. Para realizar essa anÃlise, desenvolveu-se um programa de fluxo de potÃncia trifÃsico na linguagem MATLAB. O programa à baseado na tÃcnica iterativa de escada. Foram implementados nesse programa modelos de linhas de distribuiÃÃo aÃreas e subterrÃneas, modelos de cargas concentradas e distribuÃdas conectadas em delta e em estrela, modelos de reguladores de tensÃo, modelos de banco de capacitores, modelo de transformadores trifÃsicos e o modelo do veÃculo elÃtrico. Esse modelo permite simular o veÃculo elÃtrico Tesla Roadster da Tesla Motors. O sistema teste utilizado em todas as simulaÃÃes foi o sistema IEEE 13 barras. A metodologia utilizada consistiu em simular o sistema sem regulador de tensÃo e com o regulador de tensÃo, em carga pesada e em carga leve. O veÃculo elÃtrico foi conectado a uma barra do sistema e considerou-se que o mesmo podia funcionar como carga ou gerador distribuÃdo sem e com controle de tensÃo de sequÃncia positiva no ponto de conexÃo. Adotou-se disposiÃÃes constantes de veÃculos elÃtricos para os casos de carga pesada e carga leve. Os resultados das simulaÃÃes revelam que houve violaÃÃo de tensÃo devido à inserÃÃo de veÃculos elÃtricos atuando como carga no sistema teste em carga pesada sem regulador de tensÃo. Jà quando operam como gerador, os veÃculos elÃtricos diminuem o grau de desequilÃbrio em mÃdia, podendo mantÃ-lo abaixo do limite permitido de 2 %, tornando assim as tensÃes das barras trifÃsicas do sistema mais equilibradas. Houve reduÃÃes significativas quando os veÃculos elÃtricos atuaram como carga (71,1 %) e como gerador (77,5 %) na perda de potÃncia ativa total do sistema quando o sistema operou com regulador de tensÃo na subestaÃÃo e os veÃculos elÃtricos operaram com controle de tensÃo de sequÃncia positiva (especificada em 1,0 pu).

This work is aimed to design power supply for nodes of wireless sensors networks using solar energy in indoor spaces. The proposal is made for the particular layout, but the process described can be applied generally. The result is the proposed involvement of the operating power circuit for node of wireless sensor network used indoors.

With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements, but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. Recently, data centers have replaced the 12V DC server rack distribution with a 48V DC distribution, producing a significant overall system efficiency improvement. However, 48V rack architecture raises significant challenges for the voltage regulator modules (VRMs) required for powering the processor. The 48V VRM in the vicinity of the CPU needs to be designed with very high efficiency, high power density, high light-load efficiency, as well as meet all transient requirements by the CPU and GPU. Transferring the well-developed multi-phase buck converter used in the 12V VRM to the 48V distribution platform is not that simple. The buck converter operating with 48V, stepping down to sub 2V, will be subjected to significant switching related loss, resulting in lower overall system efficiency. These challenges drive the need to look for more efficient architectures for 48V VRM solutions. Two-stage conversions can help solve the design challenges for 48V VRMs. A first-stage unregulated converter is used to step-down the 48V to a specific intermediate bus voltage. This voltage will feed a multi-phase buck converter that powers the CPU. An unregulated LLC converter is used for the first-stage converter, with zero voltage switching (ZVS) operation for the primary side switches, and zero current switching (ZCS) along with ZVS operation, for the secondary side synchronous rectifiers (SRs). The LLC converter can operate at high frequency, in order to reduce the magnetic components size, while achieving high-efficiency. The high-efficiency first-stage, along with the scalability and high bandwidth control of the second-stage, allows this architecture to achieve high-efficiency and power density. This architecture is simpler to adopt by industry, by plugging the unregulated converter before the existing multi-phase buck converters on today's platforms. The first challenge for this architecture is the transformer design of the first-stage LLC converter. It must avoid all of the loss associated with high frequency operations, and still achieve high power density without scarifying efficiency. In this thesis, the integrated matrix transformer structure is optimized by SR integration with windings, interleaved primary side termination, and a better PCB winding arrangement to achieve high-efficiency and power density, and minimize the losses associated with high-frequency operations. The second challenge is the light load efficiency improvement. In this thesis a light load efficiency improvement is proposed by a dynamic change of the intermediate bus voltage, resulting in more than 8 % light load efficiency improvements. The third challenge is the selection of the optimal bus voltage for the two-stage architecture. The impact of different bus voltages was analyzed in order to maximize the overall conversion efficiency. Multiple 48V unregulated converters were designed with maximum efficiency >98 %, and power densities >1000 W/in3, with different output voltages, to select the optimal bus voltage for the two-stage VRM. Although the two-stage VRM is more scalable and simpler to design and adopt by current industry, the efficiency will reduce as full power flows in two cascaded DC/DC converters. Single-stage conversion can achieve higher-efficiency and power-density. In this thesis, a quasi-parallel Sigma converter is proposed for the 48V VRM application. In this structure, the power is shared between two converters, resulting in higher conversion efficiency. With the aid of an optimized integrated magnetic design, a Sigma converter suitable for narrow voltage range applications was designed with 420 W/in3 and a maximum efficiency of 94 %. Later, another Sigma converter suitable for wide voltage range applications was designed with 700W/in3 and a maximum efficiency of 95 %. Both designs can achieve higher efficiency than the two-stage VRM and all other state-of-art solutions. The challenges associated with the Sigma converter, such as startup and closed loop control were addressed, in order to make it a viable solution for the VRM application. The 48V rack architecture requires regulated 12V output converters for various loads. In this thesis, a regulated LLC is used to design a high-efficiency and power-density 48V bus converter. A novel integration method of the inductor and transformer helps the LLC achieve the required regulation capability with minimum losses, resulting in a converter that can provide 1KW of continuous power with efficiency of 97.8 % and 700 W/in3 power density. This dissertation discusses new power architectures with an optimized design for the 48V rack architectures. With the academic contributions in this dissertation, different conversion architectures can be utilized for 48V VRM solutions that solve all of the challenges associated with it, such as scalability, high-efficiency, high density, and high BW control. / Doctor of Philosophy / With the rapid increase of cloud computing and the high demand for digital content, it is estimated that the power consumption of the IT industry will reach 10 % of the total electric power in the USA by 2020. Multi-core processors (CPUs) and graphics processing units (GPUs) are the key elements in fulfilling all of the digital content requirements but come with a price of more power-hungry processors, driving the power per server rack to 20 KW levels. The need for more efficient power management solutions on the architecture level, down to the converter level, is inevitable. The data center manufacturers have recently adopted a more efficient architecture that supplies a 48V DC server rack distribution instead of a 12V DC distribution to the server motherboard. This helped reduce costs and losses, but as a consequence, raised a challenge in the design of the DC/DC voltage regulator modules (VRM) supplied by the 48V, in order to power the CPU and GPU. In this work, different architectures will be explored for the 48V VRM, and the trade-off between them will be evaluated. The main target is to design the VRM with very high-efficiency and high-power density to reduce the cost and size of the CPU/GPU motherboards. First, a two-stage power conversion structure will be used. The benefit of this structure is that it relies on existing technology using the 12V VRM for powering the CPU. The only modification required is the addition of another converter to step the 48V to the 12V level. This architecture can be easily adopted by industry, with only small modifications required on the system design level. Secondly, a single-stage power conversion structure is proposed that achieves higher efficiency and power density compared to the two-stage approach; however, the structure is very challenging to design and to meet all requirements by the CPU/GPU applications. All of these challenges will be addressed and solved in this work. The proposed architectures will be designed using an optimized magnetic structure. These structures achieve very high efficiency and power density in their designed architectures, compared to state-of-art solutions. In addition, they can be easily manufactured using automated manufacturing processes.

The emergence of the Intel Pentium TM processor necessitates that a dedicated converter, the voltage regulator module (VRM), be physically located very close to the processor in computer power systems. The efficiency and transient response specifications of the VRM place contradictory requirements on the inductance. This dissertation discusses possible VRM inductor designs to improve efficiency without compromising transient responses. The multi-channel interleaving buck converter is the most popular topology for present VRMs. Analysis in this work shows that the small-signal model of an n-channel interleaving buck can be simplified as a single buck converter. The equivalent inductance is 1/n of the inductance in the interleaving channel. The equivalent switching frequency is n times the switching frequency in each channel. Through the transient response analysis, the critical inductance of the VRM is identified. The critical inductance is a tradeoff point between transient response and efficiency. The inductances smaller than the critical inductance have equal transient responses. For the inductances larger than the critical inductance, the VRM transient voltage spikes increase with the inductance. The critical inductance is the largest inductance that gives the fastest transient responses. The critical inductance is a function of the control bandwidth and the load transient steps. Although multi-channel interleaving reduces the current ripple stress on the output capacitors, it cannot reduce the current ripples in each channel. The large current ripples reduce the efficiency of the VRM. With the proposed concept of integrated coupling inductors between channels, the converters have larger equivalent inductances in steady-state operation and smaller equivalent inductances in transient response. The steady-state current ripples can be reduced without compromising the transient response. The overall efficiency of the converter is improved. In order to evaluate the application of the coupling inductor concept in multi-channels, an appropriate magnetic model is required. This dissertation proposes a flux reluctance model for the core and winding structures. With this reluctance model and mathematical transformations, the coupled inductors can be decoupled in the electric circuit simulation model. This reduces the complexity of the model when a large number of inductors are coupled. The model can be easily scaled to model the structures that involve more inductors. Examples are presented to show the application of this proposed model. / Ph. D.

One of the fundamental characteristics of the microprocessor application is its property of dynamic load change. Although idle most of the time, it wakes up in nanoseconds to support sudden workload demands, which are becoming increasingly severe in today's multi-core processors with large core count. From the standpoint of its voltage regulator (VR) design, it must have very good efficiency at light loads, while also supporting a very fast transient response. Thus, the variable-frequency constant on-time current-mode (COTCM) control scheme is widely used in the VRs, as it can automatically reduce its switching frequency during light-load conditions. But, from transient point of view, it has some limitations in response to heavy-load demands by microprocessors; this is resolved by adding different nonlinear controls in state-of-the-art control schemes. These nonlinear controls are difficult to optimize for the widely variable transient conditions in processors. Another major issue for this ripple-based COTCM control is that when the combined inductor-current ripple in multiphase operation becomes zero because of the ripple-cancellation effect, COTCM loses its controllability. Therefore, the goal of this research is to discover a new adaptive COT control scheme that is concurrently very efficient at light-load conditions and also provides a fast and optimized transient response without adding any nonlinear control; hence providing a complete solution for today's high-performance microprocessors. Firstly, the overview of state-of-the-art COTCM control is discussed in detail, and its limitations are analyzed. Analysis shows that one issue plaguing the COTCM control is its slow transient response in both single and multiphase operation. In this context, two methods have been proposed to improve the transient performance of conventional COTCM control in single and multiphase operations. These two methods can effectively reduce the output capacitor count in system, but the ripple-cancellation and phase overlapping issues in multiphase operation are yet to be improved. This provides motivation to search for a new COT control technique that can resolve all these problems together. Therefore, a new concept of inverse charge constant on-time (IQCOT) control is proposed to replace the conventional ripple-based COTCM; the goals are to improve noise immunity at the ripple-cancellation point without adding any external ramp into the system, and to improve the load step-up transient performance in multiphase operation by achieving natural and linear pulse overlapping without adding any nonlinear control. Additionally, the transient performance of the proposed IQCOT has been further improved by naturally increasing or decreasing the TON time during the load step-up or step-down transient period without adding any nonlinear control. As this transient property is inherent in proposed IQCOT control, it is adaptive to the widely variable transient requirements of processors, and always produces an optimized transient response. In order to design the proposed control with high bandwidth for supporting fast transient response, an accurate high-frequency small-signal model needs to be derived. Therefore, a high-frequency model for the proposed IQCOT control is derived using the describing function method. The model is also verified by simulation and hardware results in different operating conditions. From the derived model it is found that the quality factor (Q) of one double-pole set varies with changes in duty cycle. To overcome this challenge, an auto-tuning method for Q-value control is also proposed in this dissertation. / Ph. D.