This thesis presents the design, implementation, and fabrication of a pattern-guided equalizer in a 65nm CMOS process. By counting the occurrence of 6 out of 16 4-bit patterns in the received data and utilizing their spectral content, the signal is equalized separately at fN and fN/2, where fN is half the bit rate. The design was packaged using a 64 pin Quad Flat No leads (QFN) package. Two different channels were used and the equalizer was able to open the eye for both 13dB and 17dB of attenuation at the Nyquist frequency. The adaptation performance was determined by measuring the vertical and horizontal eye openings for all possible equalizer coefficients. Measured results at 6Gb/s confirm that the adaptation engine opens a closed eye to within 2.6% of optimal vertical opening and 7% of optimal horizontal eye opening while consuming 16.8mW from a 1.2V supply.

This thesis presents the design, implementation, and fabrication of a pattern-guided equalizer in a 65nm CMOS process. By counting the occurrence of 6 out of 16 4-bit patterns in the received data and utilizing their spectral content, the signal is equalized separately at fN and fN/2, where fN is half the bit rate. The design was packaged using a 64 pin Quad Flat No leads (QFN) package. Two different channels were used and the equalizer was able to open the eye for both 13dB and 17dB of attenuation at the Nyquist frequency. The adaptation performance was determined by measuring the vertical and horizontal eye openings for all possible equalizer coefficients. Measured results at 6Gb/s confirm that the adaptation engine opens a closed eye to within 2.6% of optimal vertical opening and 7% of optimal horizontal eye opening while consuming 16.8mW from a 1.2V supply.

The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on data communication circuits. As data rates enter the multi-Gb/s range, serial data communication architectures become attractive as compared to parallel architectures. Serial architectures have long been used in fibre optic systems for long-haul applications, however, in the past decade there has been a trend towards multi-Gb/s backplane interconnects. The integration of clock and data recovery (CDR) circuits into monolithic integrated circuits (ICs) is attractive as it improves performance and reduces the system cost, however it also introduces new challenges, one of which is robustness. In serial data communication systems the CDR circuit is responsible for recovering the data from an incoming data stream. In recent years there has been a great deal of research into integrating CDR circuits into monolithic ICs. Most research has focused on increasing the bandwidth of the circuits, however in order to integrate multi-Gb/s CDR circuits robustness, as well as performance, must be considered. In this thesis CDR circuits are analyzed with respect to their robustness. The phase detector is a critical block in a CDR circuit and its robustness will play a significant role in determining the overall performance in the presence of process non-idealities. Several phase detector architectures are analyzed to determine the effects of process non-idealities. Static phase offsets are introduced as a figure of merit for phase detectors and a mathematical framework is described to characterize the negative effects of static phase offsets on CDR circuits. Two approaches are taken to improve the robustness of CDR circuits. First, calibration circuits are introduced which correct for static phase offsets in CDR circuits. Secondly, phase detector circuits are introduced which have been designed to optimize both performance and robustness. Several prototype chips which implement these schemes will be described and measured results will be presented. These results show that while CDR circuits are vulnerable to the effects of process non-idealities, there are circuit techniques which can mitigate many of these concerns.

The bandwidth demands of modern computing systems have been continually increasing and the recent focus on parallel processing will only increase the demands placed on data communication circuits. As data rates enter the multi-Gb/s range, serial data communication architectures become attractive as compared to parallel architectures. Serial architectures have long been used in fibre optic systems for long-haul applications, however, in the past decade there has been a trend towards multi-Gb/s backplane interconnects. The integration of clock and data recovery (CDR) circuits into monolithic integrated circuits (ICs) is attractive as it improves performance and reduces the system cost, however it also introduces new challenges, one of which is robustness. In serial data communication systems the CDR circuit is responsible for recovering the data from an incoming data stream. In recent years there has been a great deal of research into integrating CDR circuits into monolithic ICs. Most research has focused on increasing the bandwidth of the circuits, however in order to integrate multi-Gb/s CDR circuits robustness, as well as performance, must be considered. In this thesis CDR circuits are analyzed with respect to their robustness. The phase detector is a critical block in a CDR circuit and its robustness will play a significant role in determining the overall performance in the presence of process non-idealities. Several phase detector architectures are analyzed to determine the effects of process non-idealities. Static phase offsets are introduced as a figure of merit for phase detectors and a mathematical framework is described to characterize the negative effects of static phase offsets on CDR circuits. Two approaches are taken to improve the robustness of CDR circuits. First, calibration circuits are introduced which correct for static phase offsets in CDR circuits. Secondly, phase detector circuits are introduced which have been designed to optimize both performance and robustness. Several prototype chips which implement these schemes will be described and measured results will be presented. These results show that while CDR circuits are vulnerable to the effects of process non-idealities, there are circuit techniques which can mitigate many of these concerns.

The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs. We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank.

The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs. We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank.

The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and analysis of devices and circuits used in this versatile system in CMOS technology. Of these blocks, we have identified the voltage-controlled oscillator (VCO) as an important circuit that contributes to the total noise performance of the CDR. Among different solutions known for this circuit, LC-VCO is acknowledged to have the best phase noise performance, due to the filtering characteristic of the LC tank circuit. We provide details on modelling and characterization of a special type of varactor, the accumulation-mode MOS varactor, used in the tank circuit as a tuning component of these types of VCOs. We propose a new sub-circuit model for this type of varactor, which can be easily migrated to other technologies as long as an accurate model exists for MOS transistors. The model is suitable whenever the numerical models have convergence problems and/or are not defined for the specific designs (e.g., minimum length structures). The model is verified directly using measurement in a standard CMOS 0.13µm process, and indirectly by comparing the tuning curves of an LC-VCO designed in CMOS 0.13µm and 0.18µm processes. Using a varactor, a circuit technique is proposed for designing a narrowband tuneable clock buffer, which can be used in a variety of applications including the CDR system. The buffer automatically adjusts its driving bandwidth to that of the VCO, using the same control voltage that controls the frequency of the VCO. In addition, a detailed analysis of the impact of large output signals on the tuning characteristics of the LC-VCO is performed. It is shown that the oscillation frequency of the VCO deviates from that of an LC tank. / Applied Science, Faculty of / Electrical and Computer Engineering, Department of / Graduate

Advances in technology and the introduction of high speed processors have increased the demand for fast, compact and commercial methods for transferring large amounts of data. The next generation of the communication access network will use optical fiber as a media for data transmission to the subscriber. In optical data or chip-to-chip data communication, the continuous received data needs to be converted to discrete data. For the conversion, a synchronous clock and data are required. A clock and data recovery (CDR) circuit recovers the phase information from the data and generates the in-phase clock and data. In this dissertation, two clock and data recovery circuits for Giga-bits per second (Gbps) serial data communication are designed and fabricated in 180nm and 90nm CMOS technology. The primary objective was to reduce the circuit power dissipation for multi-channel data communication applications. The power saving is achieved using low swing voltage signaling scheme. Furthermore, a novel low input swing Alexander phase detector is introduced. The proposed phase detector reduces the power consumption at the transmitter and receiver blocks. The circuit demonstrates a low power dissipation of 340µW/Gbps in 90nm CMOS technology. The CDR is able to recover the input signal swing of 35mVp. The peak-to-peak jitter is 21ps and RMS jitter is 2.5ps. Total core area excluding pads is approximately 0.01mm2.

Advances in technology and the introduction of high speed processors have increased the demand for fast, compact and commercial methods for transferring large amounts of data. The next generation of the communication access network will use optical fiber as a media for data transmission to the subscriber. In optical data or chip-to-chip data communication, the continuous received data needs to be converted to discrete data. For the conversion, a synchronous clock and data are required. A clock and data recovery (CDR) circuit recovers the phase information from the data and generates the in-phase clock and data. In this dissertation, two clock and data recovery circuits for Giga-bits per second (Gbps) serial data communication are designed and fabricated in 180nm and 90nm CMOS technology. The primary objective was to reduce the circuit power dissipation for multi-channel data communication applications. The power saving is achieved using low swing voltage signaling scheme. Furthermore, a novel low input swing Alexander phase detector is introduced. The proposed phase detector reduces the power consumption at the transmitter and receiver blocks. The circuit demonstrates a low power dissipation of 340µW/Gbps in 90nm CMOS technology. The CDR is able to recover the input signal swing of 35mVp. The peak-to-peak jitter is 21ps and RMS jitter is 2.5ps. Total core area excluding pads is approximately 0.01mm2.

Clock and data recovery (CDR) circuit and frequency synthesizer are two essential timing circuits in wireline and wireless communication systems, respectively. With multigigabits/s high speed links and emerging 4G wireless system widely used in communication backbone infrastructures and consumer electronic devices, effective design of CDR and frequency synthesizer has become more and more important. The advanced scaled-down CMOS process has the limitations of leakage current, low supply voltage and process variation which pose great challenge to the analog circuit design. To overcome these issues, a digital intensive CDR solution is needed. Besides, it is desirable for the CDR to cover a wide range of data-rate and to be reference-less for improved flexibility. As for the frequency synthesizer design, the support for multi-standard to reduce the cost and area is desirable. In this work, a digital reference-less CDR is proposed to support continuous datarate ranging from 1 Gbps to 16 Gbps. The CDR adopts an 8 GHz~16 GHz DCO to achieve low random noise performance. A reference-less digital frequency locking loop is included in the system as the acquisition assistance for the CDR loop. To address the difficulty of jitter and stability evaluations for bang-band CDR, a Simulink model is developed to find out the jitter transfer (JTRAN), jitter generation (JGEN) and jitter tolerance (JTOL) performances for the CDR. The prototype CDR is implemented in a 65 nm CMOS process. The core area is 0.68 mm². At 16 Gbps, the CDR consumes a power of 92.5 mW and is able to tolerate a sinusoidal jitter with an amplitude of 0.4 UI and a frequency of 4 MHz. The second part of this dissertation develops a frequency synthesizer for multistandard wireless receivers. The frequency synthesizer is based on an analog fractional-N PLL. Optimally-coupled quadrature voltage-controlled-oscillator (QVCO), dividers and harmonic rejection single sideband mixer (HR-SSBmixer) are combined to synthesize the desired frequency range without posing much phase noise penalty on the QVCO. The QVCO adopts a new phase-shift scheme to improve phase noise and to eliminate bimodal oscillation. Combining harmonic rejection and single sideband mixing, the HR-SSBmixer is developed to suppress spurious signals. Designed in a 0.13-μm CMOS technology, the synthesizer occupies an active area of 1.86 mm² and consumes 35.6 to 52.62 mW of power. Measurement results show that the synthesizer frequency range, the phase noise, the settling time and the spur performances meet the specifications of the wireless receivers for the above standards. For a wide range frequency synthesizer, an automatic frequency calibration circuit (AFC) is needed to select proper oscillator tuning curve before the PLL settling. An improved counter-based AFC is proposed in this dissertation that provides a more robust and faster tuning curve searching process. The proposed AFC adopts a time-to-digital converter (TDC), which is able to captures the fractional VCO cycle information within the counting window, to improve the AFC frequency detection accuracy. The TDC-based AFC is designed in a 0.13-μm CMOS technology. Simulation results show that the TDCbased AFC greatly improves the frequency detection accuracy and consequently for a given frequency detection resolution reduces the AFC calibration time.