This thesis presents a low power consumption and low phase noise CMOS integer-N frequency synthesizer, and it bases on a charge-pump PLL topology. The frequency synthesizer can be used for IEEE 802.16b unlicensed band of WiMAX(World Interoperability for Microwave Access) from 5.725GHz to 5.825GHz. It provides the one ration frequency ranged from 5.13GHz to 5.22GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage-controlled oscillator, and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator to achieve low power consumption and low phase noise. Moreover divider is implemented by an optimal extended true single-phase clock-base prescaler. It can achieve high-resolution frequency operation and reduction of power consumption. This chip is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The whole chip area is 1.1 mm2.

This thesis presents the CMOS integer-N frequency synthesizer for 5 GHz WCDMA applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection, and a pulse-swallow divider. In pulse-swallow divider, this thesis use true single phase clock DFF proposed by Yuan and Svensson to work on high frequency region and to save the circuit area and power. This thesis also proposes an auto-band selection circuit to control the output frequency more precise and easier, and it can also reduce the frequency drift effect caused by technology process or temperature variation.

This thesis presents a low power consumption, low phase noise, and fast locking CMOS fractional-N frequency synthesizer with optimalied voltage-controlled oscillator. The frequency synthesizer is designed in a TSMC 0.18£gm CMOS 1P6M technology process. It can be used for IEEE 802.16e mobile Wimax¡¦s devices and outputing frequency is ranged from 2.3GHz to 2.45GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump (CP), a low-pass loop filter (LPF), a voltage-controlled oscillator (VCO), a multi-modulus divider, and a delta-sigma modulator (DSM). In system design, two voltage-controlled oscillators we presented to achieve low power consumption, low phase noise, and stable output swing. Delta-sigma modulator (DSM) is adopted to produce high frequency resolution, switching over frequency fast and very low phase noise. This thesis proposes a switch circuit which can reduce the lock of time of synthesizer. In the mean time it also reduces the emergence of lose lock.

No description available.

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 μm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 μm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 μm CMOS technology.

This work presents an analogue baseband (BB) chain for a magnetic tunneling junction (MTJ) based radiofrequency (RF) signal detector fully integrated in a hybrid CMOS-MTJ technology. The BB chain contains a 6 th -order gm-C low-pass filter (LPF), a BB amplifier, a comparator, and a current bank. According to measurement results, the 6 th -order LPF with a cut-off frequency of 10 MHz consumes a very low DC power of 2.41 mW. Its DC power consumption per pole of 0.4 mW is the lowest among the state-of-the-art LPFs. The LPF can be also switched on and off very fast within 110 ns. With the fast switch-ability and the low power consumption, the LPF outperforms the state of the art. Furthermore, the complete BB chain can transform a 2.5 Vpp, 5 Mbps BB signal into digital data with a bit error rate fewer than 1e−6 . The BB chain consumes 2.85mW including all bias circuits. To achieve power efficiency, the BB chain is designed to operate under an aggressive duty-cycling mode. The switch-on time of the BB chain is within 200 ns

No description available.

Phase Locked Loop (PLL) is an integral component of clock generation circuits. A third order Charge Pump PLL (CPPLL) is most widely employed PLL architecture due to its zero steady state phase error. A monolithic implementation of such a CPPLL presents numerous challenges to PLL designers, the number of such challenges vary depending on the process technology employed and the end application. One such challenge that is worth mentioning is the on-chip integration of the second order passive loop filter. The area occupied by the second order passive loop filter is mainly determined by the zero determining capacitance (CZ). A low loop bandwidth CPPLL has a higher CZ value, and hence consumes a larger die area than a large loop bandwidth CPPLL. Literature survey shows that the problem of higher CZ value in low loop bandwidth CPPLL is addressed by using some form of emulation techniques. A relatively simpler emulation technique is the use of dual charge pump based loop filter. Existing dual charge pump based loop filter consume extra elements (such as summer that need opamps to realize the summer function) for achieving low CZ value. These extra elements consume extra area and additional power. We present two types of Summer-Less Dual Charge Pump (SDCP) based loop filter designs that do not need extra elements and still achieves low CZ value and this is achieved by using a second charge pump in an appropriate way. A test chip was implemented in 0.13µm UMC MMRFCMOS process to verify the presented circuits. The presented SDCP based loop filter circuits are particularly useful in designs employing multiple CPPLL’s and design employing low loop bandwidth CPPLL’s. Another challenge worth-mentioning is the frequency ranges over which the PLL can be locked. The Voltage Controlled Oscillator (VCO) of PLL mainly determines the frequency locking range of a PLL. A typical VCO has a frequency locking range of usually 1:2 to 1:3. The VCO frequency tuning range reduces with reduction in supply voltage. This poses a serious problem in low supply voltage applications that demand a wide frequency locking range, sometimes greater than 1:3. We have addressed this problem of wide PLL lock range, by using an Analog Frequency Detector. A wide frequency lock range is achieved, either by dynamically modifying the VCO or the feedback divider of PLL. Both the approaches are equally feasible. The frequency detector is used for dynamically modifying the VCO or the feedback divider of PLL. Two test chips were implemented to verify the presented Analog Frequency Detector scheme. A testchip implemented in 0.25µm CSM analog process achieves wide frequency lock range by dynamically modifying the feedback divider of PLL. Another testchip implemented in 0.13µm UMC MMRFCMOS process achieves wide frequency lock range by dynamically modifying the center frequency of the VCO. Presented analog frequency detection scheme is particularly useful in applications that demand wide PLL lock range from a single die.

No description available.

No description available.