Global ETD Search

1	5 GHz Phase Lock Loop with Auto Band Selection Chen, Ming-Jing 06 August 2007 (has links) This thesis presents the CMOS integer-N frequency synthesizer for 5 GHz WCDMA applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18£gm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection, and a pulse-swallow divider. In pulse-swallow divider, this thesis use true single phase clock DFF proposed by Yuan and Svensson to work on high frequency region and to save the circuit area and power. This thesis also proposes an auto-band selection circuit to control the output frequency more precise and easier, and it can also reduce the frequency drift effect caused by technology process or temperature variation. dual-modulus prescaler phase-frequency detector. Voltage-controlled oscillator auto band-selection Phase lock loop
2	A 2.5GHz Frequency Synthesizer for Mobile Device of WiMAX Shih, Ming-hung 29 July 2009 (has links) This thesis presents a low power consumption, low phase noise, and fast locking CMOS fractional-N frequency synthesizer with optimalied voltage-controlled oscillator. The frequency synthesizer is designed in a TSMC 0.18£gm CMOS 1P6M technology process. It can be used for IEEE 802.16e mobile Wimax¡¦s devices and outputing frequency is ranged from 2.3GHz to 2.45GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump (CP), a low-pass loop filter (LPF), a voltage-controlled oscillator (VCO), a multi-modulus divider, and a delta-sigma modulator (DSM). In system design, two voltage-controlled oscillators we presented to achieve low power consumption, low phase noise, and stable output swing. Delta-sigma modulator (DSM) is adopted to produce high frequency resolution, switching over frequency fast and very low phase noise. This thesis proposes a switch circuit which can reduce the lock of time of synthesizer. In the mean time it also reduces the emergence of lose lock. Frequency synthesizer PLL Charge Pump Phase Frequency Detector VCO divider Delta-sigma modulator (DSM)
3	Wide Tuning Range I/Q DCO VCO and A High Resolution PFD implementation in CMOS 90 nm Technology Suraparaju, Eswar Raju January 2015 (has links) No description available. Electrical Engineering
4	A TOP-DOWN METHODOLOGY FOR SYNTHESIS OF RF CIRCUITS VIJAY, VIKAS January 2004 (has links) No description available. Radio Frequency Synthesis Optimization Automation Layout Generation RF Analog High Frequency Module Generation C++ SKILL Extraction Performance Analysis Circuit Sizing Radio Receiver LNA Mixer VCO Phase Frequency Detector
5	Application Of Alpha Power Law Models To The PLL Design Methodology Using Behavioral Models Balssubramanian, Suresh 04 1900 (has links) (PDF) No description available. Computer Aided Design Integrated Circuits Phased Locked Loop PLL Design Digital Signal Processing (DSP) Phase Frequency Detector (PFD) Voltage Controlled Oscillators (VCO) Electronic Engineering
6	Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs Laha, Soumyasanta 25 August 2015 (has links) No description available. Electrical Engineering Wireless Communication Double Gate MOSFET 60 GHz OOK Modulation and Demodulation Oscillator Power Amplifier Low Noise Amplifier RF Mixer Phase Frequency Detector 65 nm RF CMOS TRx Design
7	Temperature Compensation in CMOS Ring Oscillator Wei, Xiaohua, Zhang, Dingyufei January 2022 (has links) A digital system is often required to operate under a specific frequency. A ring oscillator can be helpful in this circumstance because it can generate a signal with a specific frequency. However, a ring oscillator is also sensitive to the environment temperature. With the increasing requirement of accuracy and stability, many approaches appear worldwide to make a temperature-insensitive ring oscillator. This thesis project presents an approach to compensate the temperature effect on a Current Starved Ring Oscillator(CSRO). More concretely, we researched how to achieve temperature compensation for CSRO in a digitally-controlled configuration. A Phase Frequency Detector (PFD) block is adapted to sense the frequency difference between the reference frequency and CSRO frequency. Two Charge Pumps (CP)are used to quantify the difference in voltage signal. A Dynamic Comparator block compares the signals from CPs. A following Bidirectional Counter block can count up or down to change the current in CSRO by a four-bit signal. In the end, the CSRO can generate an oscillating signal at the appropriate frequency after some adaptation time. This proposed circuit was realized with AMS 0.35 um CMOS technology and simulated using the Cadence tools. Power consumption, temperature compensation analysis and voltage supply compensation analysis under different temperatures are also performed in the project. Current Starved Ring Oscillator(CSRO) Temperature compensation Supply voltage compensation Stable frequency Digital controlling Phase Frequency Detector(PFD) Dynamic comparator Bidirectional counter Charge pump(CP) Frequency divider Power consumption AMS 0.35 um EDA tool Cadence Elektroteknik och elektronik

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