Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart
from being capable of handling a wide range of data rates, the transceivers should
have low power consumption (mW/Gbps) and be fully integrated. This work
discusses enabling techniques to implement such transceivers. Specifically, three
designs: (1) a 0.5-4 Gbps serial link which uses current recycling to reduce power
dissipation and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit
which uses a novel frequency detector to achieve unlimited acquisition range and
(3) a 2-4 Gbps low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented.
All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated.
Measured results obtained from the prototypes illustrate the effectiveness of the
proposed design techniques. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Dec. 2, 2011 - June 2, 2012
| Identifer | oai:union.ndltd.org:ORGSU/oai:ir.library.oregonstate.edu:1957/25855 |
| Date | 28 November 2011 |
| Creators | Inti, Rajesh |
| Contributors | Hanumolu, Pavan K. |
| Source Sets | Oregon State University |
| Language | en_US |
| Detected Language | English |
| Type | Thesis/Dissertation |
Page generated in 0.0018 seconds