In recent years, Ultra-WideBand (UWB) radio has become the most important technology for high speed data transmission in wireless personal area networks (WPAN). In this thesis, we investigate the design and implementation of the baseband receiver for the orthogonal frequency division multiplexing (OFDM) based UWB systems. The baseband signal processing algorithms include timing synchronization, frequency synchronization, channel estimation, and the zero-padded prefix. Both floating point and fixed point simulation are conducted for system design and performance verification. Then, the Verilog hardware description language is adopted for hardware implementation. The proposed design is realized by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.13 single-poly eight-metal CMOS process.

In order to mitigate the interferences between UWB systems and the existing systems, we will seek to search a variety of UWB pulse waveforms to meet Federal Communication Commission spectral mask(especially in UWB indoor environment) ,and make good use of rare spectral resources, i.e. improving spectral efficiency. In AWGN channel and under good timing synchronization we analyze direct sequence ultra-wideband (DS-UWB) multiple access system in terms of the average bit error rate (BER) in accordance with user 1¡Fon the other hand, in indoor environment we simulate the indoor multi-path fading channel by means of modified S-V channel model, and on asynchronous condition analyze the average BER of direct sequence ultra-wideband (DS-UWB) multiple access system by Rake receiver. Finally, we must seek to find some UWB pulse waveforms having good BER performance and those also meet the ¡§FCC Mask¡¨.

Ultra-wideband (UWB) radio has been proposed for physical layer standard of the future high-speed wireless personal area networks (WPAN). In this thesis, the receiver baseband signal processing and hardware implementation of a multi-band orthogonal frequency division multiplexing (MB-OFDM) system is investigated. The baseband signal processing algorithms include time domain synchronization, frequency domain synchronization, channel estimation, and zero padded process. The developed algorithms are shown to fulfill the requirements of the system specifications and are implemented using Verilog hardware description language (HDL), which is downloaded to Xilinx FPGA (Field Programmable Gate Array) for system verification.

Low cost, a high-integrated capability, and low-power consumption are the basic requirements for ultra wide band (UWB) system design in order for the system to be adopted in various commercial electronic devices in the near future. Thus, the highly integrated transceiver is trended to be manufactured by companies using the latest silicon based complimentary metal-oxide-silicon (CMOS) processes. In this dissertation, several new structural designs are proposed, which provide solutions for some crucial RF blocks in CMOS for UWB for commercial applications. In this dissertation, there is a discussion of the development, as well as an illustration, of a fully-integrated ultra-broadband transmit/receive (T/R) switch which uses nMOS transistors with deep n-well in a standard 0.18-μm CMOS process. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET’s parasitic capacitances in order to synthesize artificial transmission lines which result in low insertion loss over an extremely wide bandwidth. Within DC-10 GHz, 10-18 GHz, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0 and 2.5 dB and isolation between 32-60 dB, 25-32 dB, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. Further, there is a discussion and demonstration of a tunable Carrier-based Time-gated UWB transmitter in this dissertation which uses a broadband multiplier, a novel fully integrated single pole single throw (SPST) switch designed by the CMOS process, where a tunable instantaneous bandwidth from 500 MHz to 4 GHz is exhibited by adjusting the width of the base band impulses in time domain. The SPST switch utilizes the synthetic transmission line concept and multiple reflections technique in order to realize a flat insertion loss less than 1.5 dB from 3.1 GHz to 10.6 GHz and an extremely high isolation of more than 45 dB within this frequency range. A fully integrated complementary LC voltage control oscillator (VCO), designed with a tunable buffer, operates from 4.6 GHz to 5.9 GHz. The measurement results demonstrate that the integrated VCO has a very low phase noise of –117 dBc/ Hz at 1 MHz offset. The fully integrated VCO achieves a very high figure of merit (FOM) of 183.5 using standard CMOS process while consuming 4 mA DC current.

In recent years, the Ultra-wideband (UWB) has become one of the most important transmission technologies in the wireless personal area networks (WPAN). In this thesis, we will focus on the multi-band orthogonal frequency division multiplexing (MB-OFDM) based UWB and investigate the hardware implementation of the Fast Fourier Transform (FFT) processor required by the baseband receiver. Due to the requirement of high data rate transmission, a pipeline structure is adopted for parallel processing at a lower clock rate. The hardware implementation is first verified and simulated by using the Verilog hardware description language (HDL). Then, the proposed design is realized by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.13 £gm single-poly eight-metal CMOS process.

Despite the fact ultra-wideband (UWB) technology has been around for over 30 years, there is a newfound excitement about its potential for communications. With the advantageous qualities of multipath immunity and low power spectral density, researchers are examining fundamental questions about UWB communication systems. Majorly the whole report gives a complete picture about properties of UWB signal and its advantages and disadvantages, generation of the UWB pulse using various techniques, Modulation scheme, Test bed, applications, UWB regulations. The report mainly concerns with the survey about various techniques and also its comparison of generating UWB pulses using various components. There is a general description on various modulation and demodulation scheme that are relevant to UWB technology and its various applications concerning different fields.   This report clearly explains how UWB is far better than RFID and difference between active and passive RFID and its communication protocol, message format. Clear explanation about advantage of higher operating frequencies and low power spectral density. Properties of UWB pulse gives clear idea why we go for UWB and in near future lot of applications will discover. Generation of UWB is a tedious process and in this report readers can understand the various method of generation its advantages and its drawbacks. Modulation and demodulation scheme gives clear idea about how UWB are modulated and demodulated as well as its probability of error and in which situation which modulation is suitable. By using future testbed concept, smaller size UWB chip will be designed and used in various application efficiently. Application gives clear idea about how to take advantage of various properties.

Low cost, a high-integrated capability, and low-power consumption are the basic requirements for ultra wide band (UWB) system design in order for the system to be adopted in various commercial electronic devices in the near future. Thus, the highly integrated transceiver is trended to be manufactured by companies using the latest silicon based complimentary metal-oxide-silicon (CMOS) processes. In this dissertation, several new structural designs are proposed, which provide solutions for some crucial RF blocks in CMOS for UWB for commercial applications. In this dissertation, there is a discussion of the development, as well as an illustration, of a fully-integrated ultra-broadband transmit/receive (T/R) switch which uses nMOS transistors with deep n-well in a standard 0.18-μm CMOS process. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET’s parasitic capacitances in order to synthesize artificial transmission lines which result in low insertion loss over an extremely wide bandwidth. Within DC-10 GHz, 10-18 GHz, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0 and 2.5 dB and isolation between 32-60 dB, 25-32 dB, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. Further, there is a discussion and demonstration of a tunable Carrier-based Time-gated UWB transmitter in this dissertation which uses a broadband multiplier, a novel fully integrated single pole single throw (SPST) switch designed by the CMOS process, where a tunable instantaneous bandwidth from 500 MHz to 4 GHz is exhibited by adjusting the width of the base band impulses in time domain. The SPST switch utilizes the synthetic transmission line concept and multiple reflections technique in order to realize a flat insertion loss less than 1.5 dB from 3.1 GHz to 10.6 GHz and an extremely high isolation of more than 45 dB within this frequency range. A fully integrated complementary LC voltage control oscillator (VCO), designed with a tunable buffer, operates from 4.6 GHz to 5.9 GHz. The measurement results demonstrate that the integrated VCO has a very low phase noise of –117 dBc/ Hz at 1 MHz offset. The fully integrated VCO achieves a very high figure of merit (FOM) of 183.5 using standard CMOS process while consuming 4 mA DC current.

The low-cost low-power complementary metal-oxide semiconductor (CMOS) ultra wideband (UWB) transmitter and receiver front-ends based on impulse technology were developed. The CMOS UWB pulse generator with frequency-band tuning capability was developed, which can generate both impulse and monocycle pulse signals with variable pulse durations. The pulse generator integrates a tuning delay circuit, a square-wave generator, an impulse-forming circuit, and a pulse-shaping circuit in a single chip. When integrated with the binary phase shift keying (BPSK) modulator, the transmitter front-end can generate a positive impulse with 0.8 V, negative impulse with 0.7 V, as well as the positive/negative monocycle pulse with 0.6 – 0.8 V, all with tunable pulse durations. The UWB receiver front-end including the template pulse generator, low noise amplifier (LNA), and multiplier was developed. The cascoded common-source inductively degenerated LNA, with extended ultra-wideband ladder matching network, as well as shunt-peaking topology, was selected to form the impulse-type UWB LNA. The structure-optimized and patterned ground shield (PGS) inductors were also studied and used in LNA design to improve the LNA performance. The maximum gain of 12.4 dB was achieved over the band. For the 3-dB bandwidth, 2.6 – 9.8 GHz was achieved. The average noise figure of 5.8 dB was achieved over the entire UWB band of 3.1-10.6 GHz. The UWB multiplier based on the transconductor multiplier structure was investigated, with the shunt-peaking topology applied to achieve the pole-zero cancellation and extend the multiplier bandwidth from 2 GHz to 10 GHz. A low-cost, compact, easy-to-manufacture coplanar UWB antenna was developed that is omni-directional, radiation-efficient and has a stable UWB response. It covers the entire UWB frequency range of 3.1 – 10.6 GHz, with the return loss better than 18-dB. This novel uniplanar antenna was integrated with the developed CMOS tunable pulse generator to form the UWB transmitter front-end module. This UWB module can transmit the monocycle pulses and the signals having shape similar to the first derivative of the monocycle pulses, all with the tunable pulse durations. The proposed UWB front-ends have the potential application in short-range communication, GPR, and short-range detections.

A fully differential CMOS variable gain amplifier (VGA) has been designed for an ultra-wideband receiver. The VGA comprises of two variable gain stages followed by a post amplifier stage. The interface between the digital control block and the analog VGA is formed by a digital-to-analog converter and an exponential voltage generator. The gain of the VGA varies dB-linearly from 0 to 52 dB with respect to the control voltage. The VGA is operated in open loop with a bandwidth greater than 500 MHz throughout the gain range to cater to the requirements of the ultra-wideband system. The noise-to-power ratio of the VGA is -23.9 dB for 1Vp-p differential input signal in the low gain setting, and the equivalent input referred noise is 1.01 V2 for the high gain setting. All three stages use common mode feedback to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode requirement of the following stage. DC offset cancellation has also been incorporated to minimize the input referred DC offset caused by systematic and random mismatches in the circuit. Compensation schemes to minimize the effects of temperature, supply and process variations have been included in the design. The circuit has been designed in 0.18??m CMOS technology, and the post layout simulations are in good agreement with the schematic simulations.

Antenna diversity for transmitted reference pulse cluster (TRPC) can mitigate the multipath interference and thus greatly improve the BER performance. Different receiver and transmitter diversity schemes have been studied in this thesis, including equal gain combining (EGC), selection combining (SC), delay combining and direct sum. By numerical analysis and simulation, the BER performance of many difference diversity schemes have been compared. For receiver diversity, selection based on simplified log likelihood ratio (SLLR) is the best candicate in terms of implementation complexity and also has the best performance with 2 receivers. For more than 2 receivers, EGC has the best performance at the cost of extra power consumption. For transmitter diversity, selection based on simplified channel quality indicator (SCQI) turns out to be the best choice considering both complexity and performance. In addition, we have also proposed a new multi-user downlink scheme, pulse pattern TRPC, which shows significant performance gain over time division TRPC. / Graduate