A fully differential Complementary Metal-Oxide Semiconductor (CMOS) Variable Gain Amplifier (VGA) consisting of complementary differential pairs with source degeneration, a current gain stage with programmable current mirror, and resistor loads is designed for high frequency and low power communication applications, such as an Ultra Wideband (UWB) receiver system. The gain can be programmed from 0dB to 42dB in 2dB increments with -3dB bandwidth greater than 425MHz for the entire range of gain. The 3rd-order intercept point (IIP3) is above -13.6dBm for 1Vpp differential input and output voltages. These low distortion broadband features benefit from the large linear range of the differential pair with source degeneration and the low impedance internal nodes in the current gain stages. In addition, common-mode feedback is not required because of these low impedance nodes. Due to the power efficient complementary differential pairs in the input stage, power consumption is minimized (9.5mW) for all gain steps. The gain control scheme includes fine tuning (2dB/step) by changing the bias voltage of the proposed programmable current mirror, and coarse tuning (14dB/step) by switching on/off the source degeneration resistors in the differential pairs. A capacitive frequency compensation scheme is used to further extend the VGA bandwidth.

A fully differential CMOS variable gain amplifier (VGA) has been designed for an ultra-wideband receiver. The VGA comprises of two variable gain stages followed by a post amplifier stage. The interface between the digital control block and the analog VGA is formed by a digital-to-analog converter and an exponential voltage generator. The gain of the VGA varies dB-linearly from 0 to 52 dB with respect to the control voltage. The VGA is operated in open loop with a bandwidth greater than 500 MHz throughout the gain range to cater to the requirements of the ultra-wideband system. The noise-to-power ratio of the VGA is -23.9 dB for 1Vp-p differential input signal in the low gain setting, and the equivalent input referred noise is 1.01 V2 for the high gain setting. All three stages use common mode feedback to fix and stabilize the output DC levels at a particular voltage depending on the input common-mode requirement of the following stage. DC offset cancellation has also been incorporated to minimize the input referred DC offset caused by systematic and random mismatches in the circuit. Compensation schemes to minimize the effects of temperature, supply and process variations have been included in the design. The circuit has been designed in 0.18??m CMOS technology, and the post layout simulations are in good agreement with the schematic simulations.

Two novel ultra-low-voltage (ULV) low-power (LP) variable gain amplifiers (VGA) are presented in this paper. These amplifiers based on complementary MOS transistors operating in weak inversion region are composed of pseudo-exponential current-to-current converters and analog multipliers. The gain of the amplifiers can be controlled by an exponential function circuit. The proposed circuits have been verified with the 0.25£gm CMOS technology by HSPICE simulations. The simulation results confirm the feasibility of the proposed VGAs.

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The variable gain amplifier (VGA) is utilized in various applications of remote sensing and communication equipments. Applications of the variable gain amplifier (VGA) include radar, ultrasound, wireless communication and even speech analysis. These applications use the variable gain amplifier (VGA) to enhance dynamic performance. The purpose of the thesis work is to implement a high linearity and low noise variable gain amplifier in 150 nm CMOS technology, for an analog-front-end of a transceiver. Two different amplifier architectures are designed and compared. First architecture is an amplifier with diode connected load and second architecture is a source degenerative amplifier. The performance of the amplifier with diode connected load is lower than the source degenerative amplifier in terms of gain, power, linearity, noise and bandwidth. So, the source degenerative amplifier is selected for implementation. The three stage variable gain differential amplifier is implemented with selected architecture. The implemented three stage variable gain differential amplifier have gain range of -541.5 mdB to 22.46 dB with step size of approximately 0.3 dB and total gain steps are 78. The -3 dB bandwidth achieved is 953.3 MHz. The third harmonic distortion (HD3) is -45 dBc at 250 mV and the power is 35 mW at 1.8 V supply source.

Thanks to the advance in CMOS technology, an extensive category of applications has been migrated from traditional BJT-based processes. System-on-a-Chip (SoC) realization of digital, analog, and even high voltage devices is now a reality. To address the challenge imposed by integrating analog and high voltage devices in standard CMOS processes, this thesis aims at the design of three specific topics in particular. With regard to the contents of the thesis, first of all, the theory of linear-in-dB automatic gain control (AGC) is discussed. In succession, a linear-in-dB variable gain amplifier (VGA) is mentioned. The implementation of a Feed-forward Output Swing Prediction AGC featuring a Prediction Parallel-Detect Single-Store Peak Detector (PDSSPD) and a High Input/Output Swing VGA is also described. Furthermore, a digitally programmable gain amplifier for a ZigBee wireless receiver is also mentioned. In response to the advent of CMOS-compatible high voltage tolerant Bipolar-CMOS-DMOS (BCD) process, an operational amplifier for level converting operation is disclosed. A 60-V Li-ion battery charger has also been proposed, along with a novel battery charge mode, namely, the incremental charge (IC) mode. Practical issues regarding the high voltage tolerant BCD process is also briefly discussed. Finally, a backplane transmitter featuring pre-emphasis and a receiver utilizing decisive feedback equalization (DFE) designed for CIC MorPack technology are presented. When packaged in a Leadless Ceramic Carrier (LCC) package, the transmitter can transmit up to 500 Mbps and the receiver can receive up to 125 Mbps, both through DuPont connectors without impedance matching.

A low-noise, variable gain amplier chain was constructed for interfa-cing a sensor to an ADC. During the course of the work two dierent methods -switched-capacitor circuits and chopping circuits - for dealing with 1/f noise wereinvestigated during the course of the work. The resulting circuit did not quitemeet the performance required by the specication, some possible improvementsare suggested.

Objective of the Master Thesis was to bring in two solutions of miniature PC display. One of them uses the VGA signal as the source of the data. The second uses USB for communication. Display using USB was chosen to be produced. Device contains LCD screen, SD card reader and audio DAC with mini speaker. Software running on the PC allows user to watch part of the screen of the computer. Position and size of the chosen part may be varied. The display may be controlled by touch screen. One part of the software running on PC is a simple video player.

Protein Vga(A) gives staphylococci resistance to streptogramins A. The recently discovered protein Vga(A)LC differs from Vga(A) only by 7 amino acid residues, but this difference is sufficient for shift of its substrate specificity towards lincosamides. The group of four amino acids in the central part of protein (LGAG in Vga(A) and SVTS in Vga(A)LC) was detected to be crucial for the substrate specificity. In this diploma thesis 5 alternativesets of vga(A)LC gene point mutations were prepared in order to determine the impact of individual amino acids of the aforementioned group on the resistance phenotype. Mutations were prepared in vector pGEM® -T and cloned into shuttle vector pRB374. The prepared constructs were transformed by electroporation into the sensitive strain of Staphylococcus aureus RN4220 and values of minimum inhibitory concentration (MIC) were measured for lincomycin, clindamycin and pristinamycin IIA by the agar dilution method. The transformation was not successful in one of the mutations. Results of setting MIC for the remaining four mutations do not make it possible to specify uniquely the ratio of individual amino acids for determining substrate specificity. Two of the amino acids were found to be important. We anticipate preparation of more mutations.