Environmental awareness has increased during the past 2-3 decades, and companies have gone from simply following legislation to adding environmental considerations into their business plans. The ongoing developments make it interesting to study how leading companies integrate environmental considerations into their product development processes. The aim of this thesis is to study how environmental considerations can be integrated into the product development process. It is based on studies made in the Swedish manufacturing industry. The research has used both quantitative and qualitative methods. The foundation for the conclusion was derived from the four different studies building this thesis. The aggregated conclusion from the studies suggests a conceptual model consisting of four cornerstones that should be addressed in order to ease the integration of environmental concerns: the management, product development process, DfE Mindset, and DfE Tools. The development of this model has its foundation in industrial case studies that show how leading companies have integrated environmental considerations in an innovative way. Combined with the conceptual model is a discussion concerning the usage of existing tools and how sub-activities carried out within the development process are less formal than before. This non-rigid structure is in line with what is suggested in current innovation research for radical innovation, since it enables creativity to flourish and does not limit designers. This freedom of action for the creativity of the personnel in the projects has raised the environmental work to a new level. The thesis also suggests how to use analytical and dialogue-based tools in a development project. It is beneficial to have a dialogue tool in the beginning of a project and in a radical innovation project, while it is beneficial to have an analytical tool later on in a project if more that one tool is used or in an incremental innovation project. / QC 20100820.

The objective of this research is to investigate low-complexity, efficient electronic equalizers to increase the data rate and possibly extend the reach of multi-mode fiber (MMF) links. Specifically, we begin by baselining the performance limits of conventional receivers. A robust, in-house mode solver was developed as part of this research and is currently being used by one of the largest fiber manufacturers in their internal R &D work. A detailed performance assessment of the impact of decision feedback equalizers has been conducted using an extensive model of the installed fiber base. The finite-length DFE results were instrumental in influencing the IEEE 802.3aq standardization effort. In particular, we were able to achieve a reach of 220m but the original goal of 300m was unattainable on 99% of the installed fiber base using DFEs of moderate complexity. A low-cost equalizer that has excellent performance, the bi-directional DFE, was applied to the MMF channel for the first time. The performance of the infinite-length BiDFE was characterized without any constraints on the signal-to-noise ratio and on the receiver front-end, as has been previously done in the literature. A new joint optimization technique that helps the finite-length BiDFE perform significantly better than the infinite-length DFE was developed. It was shown that given a finite number of filter coefficients, the BiDFE utilizes them better than the conventional DFE. Furthermore, a reach of 350-400m at a data rate of 10 Gbps was shown to be feasible with equalizers of complexity similar to that currently available. A multiple-input, multiple-output (MIMO) characterization of the MMF channel was developed through the simultaneous use of both center and offset launch together with the two-segment photo-detector. The potential benefit of MIMO processing for MMF links was demonstrated by computing Shannon capacity bounds. It was established that the 2x2 MIMO channel performs about 1.4 dBo better than the conventional 1x1 link at 10 Gbps with practical joint launch. The MIMO scheme still has a performance improvement of 1dBo at 20 Gbps thereby indicating that 20 Gbps transmission is feasible. Performance evaluation of multi-km MMF links was conducted using a comprehensive model that accounts for mode coupling effects. It was determined that ignoring mode coupling can result in under-estimation of the optimum DFE penalty by as much as 1~dBo for 1km links.

Thanks to the advance in CMOS technology, an extensive category of applications has been migrated from traditional BJT-based processes. System-on-a-Chip (SoC) realization of digital, analog, and even high voltage devices is now a reality. To address the challenge imposed by integrating analog and high voltage devices in standard CMOS processes, this thesis aims at the design of three specific topics in particular. With regard to the contents of the thesis, first of all, the theory of linear-in-dB automatic gain control (AGC) is discussed. In succession, a linear-in-dB variable gain amplifier (VGA) is mentioned. The implementation of a Feed-forward Output Swing Prediction AGC featuring a Prediction Parallel-Detect Single-Store Peak Detector (PDSSPD) and a High Input/Output Swing VGA is also described. Furthermore, a digitally programmable gain amplifier for a ZigBee wireless receiver is also mentioned. In response to the advent of CMOS-compatible high voltage tolerant Bipolar-CMOS-DMOS (BCD) process, an operational amplifier for level converting operation is disclosed. A 60-V Li-ion battery charger has also been proposed, along with a novel battery charge mode, namely, the incremental charge (IC) mode. Practical issues regarding the high voltage tolerant BCD process is also briefly discussed. Finally, a backplane transmitter featuring pre-emphasis and a receiver utilizing decisive feedback equalization (DFE) designed for CIC MorPack technology are presented. When packaged in a Leadless Ceramic Carrier (LCC) package, the transmitter can transmit up to 500 Mbps and the receiver can receive up to 125 Mbps, both through DuPont connectors without impedance matching.

Space-time block coding (STBC) has added a new dimension to broadband wireless communication systems. Applications such as wireless Internet access and multimedia require the transmission of high data rates over frequency selective fading channels. The reliability of the wireless communication system can be increased by using diversity techniques combined with an equalizer at the receiver to eliminate the inter-symbol interference caused by multipath propagation. Generalizing Alamouti's famous STBC method to frequency selective channels, Time Reversal-Space Time Block Coding (TR-STBC) was first introduced in [1] and has since been shown to be an effective transmit diversity scheme [2, 3, 4]. TR-STBC-based schemes are considered promising candidates for indoor transmission [5] as well as for the enhanced data rates of the global evolution (EDGE) system [2, 3]. The optimal equalizer for a TR-STBC-based transceiver is the Maximum Likelihood Sequence Estimator (MSLE), realized using the Viterbi algorithm. Unfortunately, a Viterbi equalizer is difficult to implement in real-time due its exponential increase in complexity with the number of antennas and the length of the channel impulse response. Thus, we consider an adaptive algorithm-based Decision Feedback Equalizer (DFE). Such a DFE requires only linear processing complexity while maintaining good performance. Theoretically, the two output streams of a 2 x 1 TR-STBC decoder are uncoupled in terms of the input signal statistics and uncorrelated in terms of the channel noise statistics. The standard approach to removing the inter-symbol interference from these streams is to use either two parallel independently-adapted Single-Input Single-Output (SISO) equalizers or to use a single Multiple-Input Multiple-Output (MIMO) equalizer. By exploiting the common second-order statistics of the two output streams, we proposea novel hybrid equalizer structure which shares the statistical information between two SISO equalizers while constraining them to have common tap weights. To accommodate various levels of performance versus computational complexity, we propose novel Least Mean Square (LMS), Normalized Least Mean Square (NLMS), and Recursive Least Squares (RLS)-based adaptive algorithms for this new equalizer architecture. We use both statistical analysis and Monte Carlo simulations to characterize the dynamic convergence of these algorithms and to compare our new structure with the conventional uncoupled SISO equalizers and fully-coupled MIMO equalizer. We show that our new equalizer outperforms the other two equalizers using a reduced computational complexity similar to the uncoupled SISO equalizers. As expected, with increasing complexity, we find that the novel RLS-based algorithms converge the fastest followed by the novel NLMS- and LMS-based algorithms. We also consider alternative packet structures and kick-start methods to increase the convergence speed and reliability of the equalizer at realistic complexity. Finally, adding multiple receiver antennas to our system, we extend our equalizer structures and algorithms to the 2 x NR case. Using analysis and simulations, we demonstrate that the added receiver diversity in this case yields even greater reliability.

The Group Research department in Tait Electronics has a reconfigurable platform for MIMO research. In particular, the platform has an adaptive multivariate DFE with the LMS algorithm currently implemented. The LMS algorithm has been simulated and optimised for implementation on the FPGA. The main objective of the research is to investigate an alternative, the RLS algorithm by comparing its performance to the LMS algorithm. The RLS algorithm is known to be more complex than the LMS algorithm but offers the potential for improved performance due to its fast-converging nature. This thesis provides a performance investigation of these adaptive filter algorithms on the MIMO system for the purpose of real-time implementation on the Tait platform. In addition to performance investigation, stability analysis and a feasibility study is shown for the RLS algorithm on the FPGA. The research is industry based and is supported by FRST.

Broadband wireless access systems can be used to deliver a variety of high data rate applications and services. Many of the channels being considered for such applications exhibit multipath propagation coupled with large delay spreads. Cur- rently, orthogonal frequency division multiplexing is employed in these channels to compensate the effect of dispersion. Single carrier (SC) modulation in conjunc- tion with frequency-domain equalization (FDE) at the receiver has been shown to be a practical alternate solution as it has lower peak to average power ratio and is less sensitive to frequency offsets and phase noise compared to OFDM. The effect of multipath propagation increases with increasing data rate for SC systems. This leads to larger inter-symbol-interference (ISI) spans. In addition the achievable ca- pacity of SC-broadband systems depends on their ability to accommodate multiple signal transmissions in the same frequency band, which results in co-channel inter- ference (CCI) when detecting the desired data stream. The effects of CCI and ISI are more pronounced at high data rates. The objective of this research is to investi- gate and a develop low-complexity frequency domain receiver architectures capable of suppressing both CCI and ISI and employing practical channel estimation. In this thesis, a linear and a non-linear receiver architecture are developed in the frequency domain for use in highly dispersive channels employing multiple input multiple output (MIMO) antennas. The linear receiver consists of parallel branches each corresponding to a transmit data stream and implements linear equalization and demodulation. Frequency domain joint CCI mitigation and ISI equalization is implemented based on estimated channel parameters and is called space-frequency Broadband wireless access systems can be used to deliver a variety of high data rate applications and services. Many of the channels being considered for such applications exhibit multipath propagation coupled with large delay spreads. Cur- rently, orthogonal frequency division multiplexing is employed in these channels to compensate the effect of dispersion. Single carrier (SC) modulation in conjunc- tion with frequency-domain equalization (FDE) at the receiver has been shown to be a practical alternate solution as it has lower peak to average power ratio and is less sensitive to frequency offsets and phase noise compared to OFDM. The effect of multipath propagation increases with increasing data rate for SC systems. This leads to larger inter-symbol-interference (ISI) spans. In addition the achievable ca- pacity of SC-broadband systems depends on their ability to accommodate multiple signal transmissions in the same frequency band, which results in co-channel inter- ference (CCI) when detecting the desired data stream. The effects of CCI and ISI are more pronounced at high data rates. The objective of this research is to investi- gate and a develop low-complexity frequency domain receiver architectures capable of suppressing both CCI and ISI and employing practical channel estimation. In this thesis, a linear and a non-linear receiver architecture are developed in the frequency domain for use in highly dispersive channels employing multiple input multiple output (MIMO) antennas. The linear receiver consists of parallel branches each corresponding to a transmit data stream and implements linear equalization and demodulation. Frequency domain joint CCI mitigation and ISI equalization is implemented based on estimated channel parameters and is called space-frequency

This paper investigates the effect of parameter selection for the decision feedback equalization (DFE) on communication performance through a dispersive underwater acoustic wireless channel (UAWC). A DFE based on minimum mean-square error (MMSE-DFE) criterion has been employed in the implementation for evaluation purposes. The output from the MMSE-DFE is input to the decoder to estimate the transmitted bit sequence. The main goal of this experimental simulation is to determine the best selection, such that the reduction in the computational overload is achieved without altering the performance of the system, where the computational complexity can be reduced by selecting an equalizer with a proper length. The system performance is tested for BPSK, QPSK, 8PSK and 16QAM modulation and a simulation for the system is carried out for Proakis channel A and real underwater wireless acoustic channel estimated during SPACE08 measurements to verify the selection.

Como resultado del constante aumento del tráfico de información, en los últimos años la industria de las telecomunicaciones ha evolucionado de manera vertiginosa. Este hecho exige el diseño de nuevos transceptores de comunicaciones digitales que permitan aumentar la velocidad de procesamiento. Este incremento de velocidad en combinación con las limitaciones del ancho de banda del canal de comunicaciones, exacerban los efectos de la interferencia inter-símbolo (Intersymbol Interference - ISI). Para compensar este efecto se requiere implementar en el receptor potentes esquemas de ecualización. El ecualizador realimentado por decisiones (Decison Feedback Equalizer - DFE) representa una de técnicas de ecualización más utilizadas en la industria. El DFE se caracteriza por tener una buena relación entre desempeño y complejidad. Desafortunadamente, su aplicación en sistemas de alta velocidad ha sido limitada debido a la elevada complejidad que aparece cuando se utilizan técnicas de procesamiento en paralelo como resultado de la existencia de lazos realimentados. En particular, la complejidad de las técnicas existentes incrementa exponencialmente con la memoria del canal. Esto lleva a restringir el uso de este tipo de ecualizadores para una ISI moderada. La presente Tesis propone un nuevo esquema de ecualización iterativo de complejidad reducida para receptores de alta velocidad. El nuevo ecualizador directo asistido por decisiones (Decision FeedForward Equalizer - DFFE) permite obtener un rendimiento similar al DFE pero con una arquitectura paralelizable cuya complejidad aumenta cuadráticamente con la memoria del canal. Para canales con gran ISI, esto se traduce en una drástica reducción de la complejidad en comparación con el DFE. La idea central detrás del DFFE, es la iteración de decisiones tentativas para mejorar la precisión de la estimación de la ISI. Para investigar el desempeño del nuevo receptor se desarrolla un estudio teórico y se lo verifica por exhaustivas simulaciones en computadora. Como una segunda contribución de la Tesis se presenta un detallado análisis de complejidad del procesamiento y además se realiza la implementación en FPGA del DFFE en paralelo. Este estudio permite demostrar los importantes beneficios que tiene utilizar una arquitectura de implementación directa (forward) y además verificar experimentalmente el desempeño del DFFE. Todas estas ventajas convierten al DFFE en una excelente opción para receptores de sistemas de comunicaciones digitales de alta velocidad. / As a result of the steady increase in data traffic, the telecommunications industry has evolved dramatically in recent years. In this context, new digital communications transceivers that outperform processing speed are required. This speed increase combined with the limitations of the bandwidth communications channel exacerbate the impacts of the intersymbol interference (ISI). In order to compensate for this effect, it is necessary to implement efficient receiver equalization schemes. The decision feedback equalizer (DFE) is one of the most popular equalization techniques in industry, featuring a good relationship between performance and complexity. Unfortunately, its use in high speed systems has been limited due to the high complexity reached when processing techniques are used in parallel as a result of the existence of feedback loops. In particular, the complexity of the existing techniques increases exponentially with the channel memory, leading to a restriction in the use of such equalizers for moderate ISI. This Thesis proposes a new scheme of reduced complexity iterative equalization for high-speed receivers. The new Decision FeedForward Equalizer (DFFE) allows for a similar performance to the DFE but with a parallelizable architecture whose complexity increases quadratically with the channel memory. For channels with large ISI, this results in a drastic reduction in complexity compared to the DFE. The main feature of the DFFE is the iteration of tentative decisions to improve the accuracy of the ISI estimation. With the purpose of investigating the performance of the new receiver, a theoretical study is developed and the DFFE is verified by extensive computer simulations. The second contribution of the present Thesis is a detailed analysis of processing complexity and the implementation in FPGA of parallel DFFE. This study allows to demonstrate the important benefits of using a forward implementation architecture and verify experimentally the performance of DFFE. All these advantages make the DFFE an excellent choice for system receivers of digital high-speed communications.

Vehicle manufactures have adopted different strategies for improving the environmental performance of their fleet including lightweight design and alternative drivetrains such as EVs. Both strategies reduce energy during use but may result in a relative increase of the impact during other stages. To address this, a lifecycle approach is needed when vehicle design strategies are developed. The thesis explores the extent that such a lifecycle approach is adopted today and assesses the potential of these strategies to reduce the lifecycle impact of vehicles. Moreover it aims to contribute to method development for lifecycle considerations during product development and material selection. Current practices were explored in an empirical study with four vehicle manufacturers. The availability of tools for identifying, monitoring and assessing design strategies was explored in a literature review. The results of the empirical study showed that environmental considerations during product development often lack a lifecycle perspective. Regarding the use of tools a limited number of such tools were utilized systematically by the studied companies despite the numerous tools available in literature. The influence of new design strategies on the lifecycle environmental performance of vehicles was assessed in three case studies; two looking into lightweight design and one at EVs. Both strategies resulted in energy and GHG emissions savings though the impact during manufacturing increases due to the advanced materials used. Assumptions relating to the operating conditions of the vehicle e.g. lifetime distance or for EVs the carbon intensity of the energy mix, influence the level of this tradeoff. Despite its low share in terms of environmental impact EOL is important in the overall performance of vehicles. The thesis contributed to method development by suggesting a systematic approach for material selection. The approach combines material and environmental analysis tools thus increases the possibilities for lifecycle improvements while minimizing risk for sub-optimizations. / <p>QC 20160920</p>

O aumento das exigências ambientais pela sociedade, mercado e legislação vem forçando os acadêmicos a buscarem formas de reduzir os impactos ambientais do produto durante todo o seu ciclo de vida. A integração de ferramentas de ecodesign no Processo de Desenvolvimento de Produtos (PDP) visa melhorar os requisitos ambientais do produto sem comprometer o seu desempenho, custo e características. Apesar dessa tendência, as estruturas de PDP não incorporam práticas ambientais de forma adequada. Assim, esse trabalho objetiva integrar práticas de ecodesign em uma estrutura de PDP. Para atingir esse propósito foi empregada uma análise sistemática da literatura mesclando técnicas de análise bibliométrica e de redes sociais, diagramas, mapeamento de 154 métodos de ecodesign, análise das características e questões ambientais de 80 estruturas de PDP e sistematização de 365 aspectos ambientais no PDP. Os resultados demonstram que as estruturas de PDP não enfatizam as fases de pré-desenvolvimento e pós-desenvolvimento que têm importância para redução do impacto ambiental. Portanto, foi elaborada uma proposta detalhada de integração analisando as características e contribuição de cada aspecto ambiental para minimizar o impacto ambiental do produto e sua relação com a função de cada tarefa do PDP. Na avaliação da proposta, verificou-se que nas fases de projeto conceitual e projeto detalhado houve menor aceitação quanto ao momento da integração dos aspectos ambientais, devido à interface dessas fases. Já no planejamento estratégico de projetos, planejamento de projeto e projeto informacional ocorreu desvio padrão alto nas notas, indicando divergência de opinião dos especialistas sobre o tema. Conclui-se que esse trabalho engloba um conjunto de práticas de ecodesign para suportar a tomada de decisão no PDP com objetivo de reduzir o impacto ambiental do produto durante todo o ciclo de vida. / The society, market and legislation demands for sustainability have grown then academics have to revisit the issue and to search for ways to reduce the environmental impact of the product during its life cycle. The integration of ecodesign tools in the Product Development Process (PDP) aiming at the improvement the product environmental requirements without compromising its performance, cost or characteristics. However, in spite of this tendency, the structures of PDP still do not incorporate environmental practices in their activities in a proper manner. Therefore, the proposal of this work is integrating ecodesign practices in the tasks of PDP structure. To achieve this purpose was used the systematic literature review linking techniques such as bibliometric and social networking analysis, diagrams, mapping 154 ecodesign methods, analysis of the characteristics and environmental issues of 80 PDP structures and systematization of 365 environmental aspects in the PDP. The results demonstrate that the PDP structures do not emphasize the phases of pre-development and post-development that are important to reduce environmental impact. Therefore, a detailed proposal for integration was developed by analyzing the characteristics and contribution of each environmental aspect to minimize the environmental impact of the product and its relation to the function of each task of the PDP. In assessing the proposal, it was found that the phases of conceptual design and detailed design were less accepted about time of integration of environmental aspects, due to the interface of these phases. In the strategic planning of projects, project planning and informational project were a high standard deviation in the experts evaluation, indicating divergence of opinion on the theme. In conclusion, this work includes a set of ecodesign practices to support decision making in the PDP in order to reduce the environmental impact of the product throughout its life cycle.