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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

A 3.3V 8-bit 250MHzS/s 14mW Current Mode Analog to Digital Converter Using Synchronous Comparison

Fan, Gang-Jin 19 July 2005 (has links)
A 3.3V 8-bit 250MSample/sec synchronous comparison current-mode analog to digital converter is described in this thesis. The high bits and low bits are realized by two 4-bit synchronous comparison A/Ds. The 4-bit ADC has 4 reference output, which are compared with Iin, to carry out 4-bit synchronous digital output. The reference produce circuit architecture comprises a quantification current source circuit and a thermal-to-analog (DAC) circuit. In this IADC architecture, each 4-bit pipelined stage consists of current-mirror circuits, quantification current source, and current comparator elements. This architecture can achieve a very high conversion rate due to the lack of sample/hold circuit. From HSPICE simulation results, the proposed IADC can achieve 8-bit resolution with 250MHz sampling rate. It is designed by using TSMC 0.35£gm COMS 2P4M technology. It occupies an area of 420um ¡Ñ 550um and has power consumption of 13.24mW from a 3.3-V supply. That DNL is +/- 0.5LSB, and INL is +/- 0.65LSB are achieved. Source : VLSI 2005 submitted.

A 3.3V 10-bit 50-MS/s Pipelined Analog-to-Digital Converter with Low-Deviation MDAC

Wang, Chun-Ta 14 July 2004 (has links)
A 10-bit 50MSample/sec pipelined analog-to-digital converter is described in this thesis. We replaced conventional multiplying digital-to-analog converter with low-deviation multiplying digital-to-analog converter in the proposed pipelined analog-to-digital converter. Using nonregular feedback capacitors achieves better linearity than using conventional regular feedback capacitors in the multiplying digital-to-analog converter. The accuracy of this pipelined analog-to-digital converter can be also improved, the result shows that the DNL is ¡Ó0.31 LSB, INL is about ¡Ó0.57LSB. Our proposed pipelined analog-to-digital converter is designed by TSMC 2P4M 0.35um process. It operates at 3.3V power supply voltage with 0.5 to 2.5V reference voltage, and the power consumption is about 64mW.


Ceekala, Mithun 23 April 2013 (has links)
This thesis presents a new architecture of stochastic Analog-to-Digital converter (ADC). A standard Stochastic ADC uses comparator random offset as the trip point while all the comparators have the same reference voltages. Since the offset of a basic comparator depends on a number of independent random variables, the offset will follow randomly distributed Gaussian function. The input dynamic range of this standard stochastic ADC is ±?. For 90nm technology ? value is around 153mV. A technique is presented that converts overall transfer function of a stochastic ADC i.e. Gaussian distribution into almost uniformly distribution with a wider range. With the proposed technique, an input dynamic range of ± 153mV and ENOB of 4bits of standard stochastic ADC are increased to variable input dynamic range of ±250mV to ±500mV and ENOB of 6bits.

Design of a low power analog to digital converter in a 130nmCMOS technology

Radhakrishnan, Venkataraman January 2011 (has links)
Communication technology has become indispensable in a modernsociety. Its importance is growing day by day. One of the main reasonsbehind this growth is the advancement in the analog and mixed signalcircuit design.Analog to digital converter (ADC) is an essential part in a modernreceiver system. Its development is driven by the progress of CMOStechnologies with an aim to reduce area and power consumption. In thearea of RF integrated circuits for wireless application low operationalvoltage, and less current consumption are the central aspects of thedesign. The aim of this master thesis is the development and design ofa low-power analog to digital converter for RF applications.The basic specifications are:· High Speed, Low Current (1.5 V supply voltage)· Maximum input frequency 3.5 MHz· 8-bit resolution· Sampling rate < 100 MHzThus, this work comprises a theoretical concept phase in whichdifferent ADC topologies will be investigated. Based on which anappropriate ADC architecture will be fixed. Later, the chosen design willbe implemented in an industrial 130 nm CMOS process.

Split Cyclic Analog to Digital Converter Using A Nonlinear Gain Stage

Spetla, Hattie 02 September 2009 (has links)
"Previous implementations of digital background calibration for cyclic ADCs have required linear amplifier behavior in the gain stage for accurate correction. Correction is digital decoding of ADC outputs to determine the original ADC input. Permitting nonlinearity in the gain stage of the ADC allows for less demanding amplifier design requirements, reducing power and size. However this requires a method of determining the value of this variable gain during digital correction. Look up tables (LUTs,) are an effective and efficient method of compensating for analog circuit imperfections. The LUT correction and calibration method discussed in this work has been simulated using Cadence integrated circuit simulation ADC specifications and MATLAB."

A prototype of a new class of oversampling adc

He, Jun 16 August 2006 (has links)
Analog-to-digital (A/D) and digital-to-analog (D/A) converters are important blocks in signal processing system because they provide the link between the analog world and digital systems. Compared with Nyquist-rate data converters, oversampling data converters are more desirable for modern submicron technologies with low voltage supplies. Today, all existing oversampling modulators in popular use are derived from sigma-delta modulation. Stability is the most significant problem in the sigma-delta modulator, because the ultimate accuracy is limited by stability. As the aggressiveness of the design increases, the margin of stability diminishes rapidly. This thesis presents the design and experimental results of the first prototype circuit implementation of the novel oversampling modulation scheme proposed by Dr. Takis Zourntos. This new class of oversampling modulators are theoretically stable. With less stability limitation, the new class of modulators can potentially achieve higher signal-to-noise ratio (SNR) or less power by designing the modulator more aggressively. This thesis describes the methods and procedures of how the new oversampling modulation theory is implemented into a circuit. Some novel circuit architectures are proposed in this modulator, such as a filter which can provide status outputs for the controller and realize arbitrary zeros and poles, comparators with synchronization latches to eliminate the effect of metastability, and a digital-to-analog converter (DAC) with current calibration circuits for high linearity. A third-order continuous-time oversampling modulator employing 4-bit quantization is implemented in a 0.35-µm double-poly complementary metal oxide semiconductor (CMOS) technology, with a chip area of 2150 × 2150 µm2. Simulation results show it achieves 83.7-dB peak SQNR, 90-dB dynamic range over a 500kHz input signal bandwidth, and 60 mW power consumption.

Design and Implementation of a Digitally Compensated N-Bit C-xC SAR ADC Model : Optimization of an Eight-Bit C-xC SAR ADC

Hallström, Claes January 2013 (has links)
In this master’s thesis a model of a digitally compensated N-bit C-xC sar adc was developed.The architecture uses charge redistribution in a C-xC capacitor network to performthe conversion. Focus in the master’s thesis was set to understand how the charge is redistributedin the network during the conversion and calibration phase. Redundancy andparasitic capacitors is present in the system and rises the need for extra conversion steps aswell as a calibration algorithm. The calibration algorithm, Bit Weight Estimation, calculatesa weight corresponding to each bit which is used in the last conversion step to perform adigital weighting. The result of extensive calculations in different C-xC capacitor networkswas a model in Python of an N-bit C-xC sar adc. That model was used to create a model ofan eight-bit C-xC sar adc and finding suitable parameters for it through calculations andsimulations. The parameters giving the best inl was chosen. With the best parameters theC-xC sar adc static and dynamic performance was tested and showed an inl of less than1lsb, snr of 47:8 dB and enob of 7:6 bits.

A study of capacitor array calibration for a successive approximation analog-to-digital converter

Ma, Ji, active 2013 07 October 2014 (has links)
Analog-to-digital converters (ADCs) are driven by rapid development of mobile communication systems to have higher speed, higher resolution and lower power consumption. Among multiple ADC architectures, successive approximation (SAR) ADCs attract great attention in mixed-signal design community recently. It is due to the fact that they do not contain amplification components and the digital logics are scaling friendly. Therefore, it is easier to design a SAR ADC with smaller component size in advanced technology than other ADC architectures, which decreases the power consumption and increases the speed of the circuit. However, capacitor mismatch limits the minimum size of unit capacitors which could be used for a SAR ADC with more than 10 bit resolution. Large capacitor both limits conversion speed and increases switching power. In this design project, a novel switching scheme and a novel calibration method are adopted to overcome the capacitor mismatch constraint. The switching scheme uses monotonic switching in a SAR ADC to gain one extra bit, and switches a dummy capacitor between the common mode voltage level (Vcm) and the ground (gnd) to obtain another extra bit. To keep the resolution constant, the capacitor number is reduced by two. The calibration method extracts missing code width to estimate the actual value of capacitors. The missing code extraction is accomplished by detecting metastable state of a comparator, forcing the current bit value and using less significant bits to measure the actual capacitor value. Dither method is adopted to improve calibration accuracy. Behavior model simulation is provided to verify the effectiveness of the calibration method. A circuit design of a 12 bit ADC and the simulation for schematic design is presented in this report. / text

A study of SAR ADC and implementation of 10-bit asynchronous design

Kardonik, Olga 13 December 2013 (has links)
Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered or mobile applications which need medium resolution (8-12 bits), medium speed (10 - 100 MS/s) and require low-power consumption and small form factor. This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC’s analog components – comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 µm. Design’s noise and power are presented as a breakdown among components. / text

A 8-bit 20-MS/s Pipeline ADC and A Low-Power 5-bit 2.4-MS/s Successive Approximation ADC for ZigBee Receivers

Cheng, Kuang-Ting 07 July 2006 (has links)
The first topic of this thesis proposes an 8-bit, 20 MSample/s pipeline analog-to-digital converter (ADC). The sharing amplifiers technique is employed to reduce the overall number of the amplifiers wherein dynamic comparators are adopted to reduce the power consumption. The proposed design is implemented by 0.35 £gm CMOS technology. The simulation results show that maximum power consumption is 45 mW given a 3.3 V power supply, and the SFDR is 45 dB with a sinusoidal input at 5 MHz. The second topic is to describe a 5-bit, 2.4 MSample/s, low power analog-to-digital converter for ZigBee receiver using 868/915 MHz band. The converter uses the successive approximation architecture. By using 0.18 £gm CMOS technology, the simulation results show the worst-case power consumption is merely 449.6 £gW. The converter achieves the maximum differential nonlinearity of 0.3 LSB, the maximum integral nonlinearity of 0.5 LSB.

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