A 3.3V 8-bit 250MSample/sec synchronous comparison current-mode analog to digital converter is described in this thesis. The high bits and low bits are realized by two 4-bit synchronous comparison A/Ds. The 4-bit ADC has 4 reference output, which are compared with Iin, to carry out 4-bit synchronous digital output. The reference produce circuit architecture comprises a quantification current source circuit and a thermal-to-analog (DAC) circuit. In this IADC architecture, each 4-bit pipelined stage consists of current-mirror circuits, quantification current source, and current comparator elements. This architecture can achieve a very high conversion rate due to the lack of sample/hold circuit. From HSPICE simulation results, the proposed IADC can achieve 8-bit resolution with 250MHz sampling rate. It is designed by using TSMC 0.35£gm COMS 2P4M technology. It occupies an area of 420um ¡Ñ 550um and has power consumption of 13.24mW from a 3.3-V supply. That DNL is +/- 0.5LSB, and INL is +/- 0.65LSB are achieved. Source : VLSI 2005 submitted.

A 10-bit 50MSample/sec pipelined analog-to-digital converter is described in this thesis. We replaced conventional multiplying digital-to-analog converter with low-deviation multiplying digital-to-analog converter in the proposed pipelined analog-to-digital converter. Using nonregular feedback capacitors achieves better linearity than using conventional regular feedback capacitors in the multiplying digital-to-analog converter. The accuracy of this pipelined analog-to-digital converter can be also improved, the result shows that the DNL is ¡Ó0.31 LSB, INL is about ¡Ó0.57LSB. Our proposed pipelined analog-to-digital converter is designed by TSMC 2P4M 0.35um process. It operates at 3.3V power supply voltage with 0.5 to 2.5V reference voltage, and the power consumption is about 64mW.

This thesis presents a new architecture of stochastic Analog-to-Digital converter (ADC). A standard Stochastic ADC uses comparator random offset as the trip point while all the comparators have the same reference voltages. Since the offset of a basic comparator depends on a number of independent random variables, the offset will follow randomly distributed Gaussian function. The input dynamic range of this standard stochastic ADC is ±?. For 90nm technology ? value is around 153mV. A technique is presented that converts overall transfer function of a stochastic ADC i.e. Gaussian distribution into almost uniformly distribution with a wider range. With the proposed technique, an input dynamic range of ± 153mV and ENOB of 4bits of standard stochastic ADC are increased to variable input dynamic range of ±250mV to ±500mV and ENOB of 6bits.

"Previous implementations of digital background calibration for cyclic ADCs have required linear amplifier behavior in the gain stage for accurate correction. Correction is digital decoding of ADC outputs to determine the original ADC input. Permitting nonlinearity in the gain stage of the ADC allows for less demanding amplifier design requirements, reducing power and size. However this requires a method of determining the value of this variable gain during digital correction. Look up tables (LUTs,) are an effective and efficient method of compensating for analog circuit imperfections. The LUT correction and calibration method discussed in this work has been simulated using Cadence integrated circuit simulation ADC specifications and MATLAB."

Communication technology has become indispensable in a modernsociety. Its importance is growing day by day. One of the main reasonsbehind this growth is the advancement in the analog and mixed signalcircuit design.Analog to digital converter (ADC) is an essential part in a modernreceiver system. Its development is driven by the progress of CMOStechnologies with an aim to reduce area and power consumption. In thearea of RF integrated circuits for wireless application low operationalvoltage, and less current consumption are the central aspects of thedesign. The aim of this master thesis is the development and design ofa low-power analog to digital converter for RF applications.The basic specifications are:· High Speed, Low Current (1.5 V supply voltage)· Maximum input frequency 3.5 MHz· 8-bit resolution· Sampling rate < 100 MHzThus, this work comprises a theoretical concept phase in whichdifferent ADC topologies will be investigated. Based on which anappropriate ADC architecture will be fixed. Later, the chosen design willbe implemented in an industrial 130 nm CMOS process.

Analog-to-digital converters (ADCs) are driven by rapid development of mobile communication systems to have higher speed, higher resolution and lower power consumption. Among multiple ADC architectures, successive approximation (SAR) ADCs attract great attention in mixed-signal design community recently. It is due to the fact that they do not contain amplification components and the digital logics are scaling friendly. Therefore, it is easier to design a SAR ADC with smaller component size in advanced technology than other ADC architectures, which decreases the power consumption and increases the speed of the circuit. However, capacitor mismatch limits the minimum size of unit capacitors which could be used for a SAR ADC with more than 10 bit resolution. Large capacitor both limits conversion speed and increases switching power. In this design project, a novel switching scheme and a novel calibration method are adopted to overcome the capacitor mismatch constraint. The switching scheme uses monotonic switching in a SAR ADC to gain one extra bit, and switches a dummy capacitor between the common mode voltage level (Vcm) and the ground (gnd) to obtain another extra bit. To keep the resolution constant, the capacitor number is reduced by two. The calibration method extracts missing code width to estimate the actual value of capacitors. The missing code extraction is accomplished by detecting metastable state of a comparator, forcing the current bit value and using less significant bits to measure the actual capacitor value. Dither method is adopted to improve calibration accuracy. Behavior model simulation is provided to verify the effectiveness of the calibration method. A circuit design of a 12 bit ADC and the simulation for schematic design is presented in this report. / text

Analog-to-Digital Converters (ADC's) are inherently optimized for linearity in order to produce an accurate digital representation of an analog voltage. The Cyclic ADC's linearity is limited by one of its components, the residue amplifier. The residue amplifier is used to amplify the error between the analog voltage and the digital decision by a gain of two in each cycle of a conversion. In previous designs, this was accomplished by using a compound op-amp with a large open loop gain for linearity, and negative feedback to achieve the gain of two. This thesis explores the use of a resistively loaded differential pair to achieve this gain. The design reduces die size, power usage, and analog complexity. To correct for this inherent non- linearity, a Split ADC concept is employed to enable digital background calibration and a correction algorithm to account for this non- linearity. The Integrated circuit is designed, laid out, and simulated using the Cadence Integrated Circuit Front to Back design suite (ICFB) in the 0.18um Jazz CMOS process.

In this MS thesis, a redundant flash analog-to-digital converter (ADC) using a ``Split-ADC' calibration structure and lookup-table-based correction is presented. ADC input capacitance is minimized through use of small, power efficient comparators; redundancy is used to tolerate the resulting large offset voltages. Correction of errors and estimation of calibration parameters are performed continuously in the background in the digital domain. The proposed flash ADC has an effective-number-of-bits (ENOB) of 6-bits and is designed for a target sampling rate of 1Gs/s in 180nm CMOS. The calibration algorithm described has been simulated in MATLAB and an FPGA implementation has been investigated.

Zielsetzung: Die Zielsetzung dieser Arbeit war es zu beurteilen, inwieweit die Diffusionsgewichtete MRT Bildgebung bei der Differenzierung zwischen malignen und benignen Erkrankungen im Kopf-Hals Bereich nützlich sein kann. Außerdem ging es um die Sammlung der mittleren ADC-Werte von verschiedenen Diagnosen. Material und Methoden: Es wurden diffusionsgewichtete Bilder mit einer SE-EPI-Sequenz (b-Wert Paarung von 50 und 800 s/mm2, 1,5T) verglichen. 53 Plattenepithelcarzinome (PeCa), 21 benigne Befunde, 6 Lymphome, 6 Hämangiome, 6 Zysten Ergebnis: Die mittlere ADC- Wert (MW x10-3mm²/s +/-SD) der PeCa betrug 0.967 (0.118), der benignen Läsionen 1.458 (0.371), der Lymphome 0.649 (0.167), der Hämangiome 1.654 (0.254), der Zysten 2.310 (0.655) Der mittlere ADC-Wert der PeCa war signifikant kleiner als der der benignen Läsionen. Ein ADC- Wert von 1.202x10-3mm²/s kann als Grenzwert für die Differenzierung zwischen benignen und malignen Läsionen im Kopf-Hals Bereich angesehen werden. Schlussfolgerung: Die ADC-Werte können für die Charakterisierung von Läsionen im Kopf-Hals Bereich genutzt werden. / Objective: The objective of this study was to evaluate the utility of diffusion weighted MR imaging (DWI) in the differentiation between malignant and benign lesions in the head and neck region. Furthermore get values for the apparent diffusion coefficient (ADC) for different diagnoses. Material and methods: We compared diffusion weighted images using SE-EPI sequences (b values of 50 and 800 s/mm2, 1,5T). 53 squamosa cell carcinomas (SSC), 21 benigne lesions, 6 malignant lymphomas, 6 hämangiomas, 6 cysts Results: The ADC values (mean x10-3mm²/s +/- SD) were 0.967 (0.118) in squamosal cell carcinomas (SSC), 1.458 (0.371) in benign lesions, 0.649 (0.167) in malignant lymphomas, 1.654 (0.254) in hämangiomas, 2.310 (0.655) in cysts. The mean ADC of SSC was significantly lower than of benign lesions. An ADC value of 1.202x10-3mm²/s may be the threshold value for differentiation between benign and malignant head and neck lesions. Conclusion: Measurement of ADCs may be used to characterize head and neck lesions.

In this master’s thesis a model of a digitally compensated N-bit C-xC sar adc was developed.The architecture uses charge redistribution in a C-xC capacitor network to performthe conversion. Focus in the master’s thesis was set to understand how the charge is redistributedin the network during the conversion and calibration phase. Redundancy andparasitic capacitors is present in the system and rises the need for extra conversion steps aswell as a calibration algorithm. The calibration algorithm, Bit Weight Estimation, calculatesa weight corresponding to each bit which is used in the last conversion step to perform adigital weighting. The result of extensive calculations in different C-xC capacitor networkswas a model in Python of an N-bit C-xC sar adc. That model was used to create a model ofan eight-bit C-xC sar adc and finding suitable parameters for it through calculations andsimulations. The parameters giving the best inl was chosen. With the best parameters theC-xC sar adc static and dynamic performance was tested and showed an inl of less than1lsb, snr of 47:8 dB and enob of 7:6 bits.