A phase-locked loop commonly known as PLL is widely used in communication systems. A PLL is used in radio, telecommunications, modulation and demodulation. It can be used for clock generation, clock recovery from data signals, clock distribution and as a frequency synthesizer. Most electronic circuits encounter the problem of the clock skew. The clock Skew for a synchronous circuit is defined as the difference in the time of arrival between two sequentially adjacent registers. The registers and the flip-flops do not receive the clock at the same time. The clock signal in a normal circuit is generated with an oscillator, oscillator produces error, due to which there is a distortion from the expected time interval. The PLLs are used to address the problem. A phase-locked loop works to ensure the time interval seen at the clocks of various registers and the flip-flops match the time intervals generated by the oscillator. PLLs are trivial and an essential part of the micro-processors. Traditional PLLs are designed to work as an analog building block, but it is difficult to integrate them on a digital chip. Analog PLLs are less affected by noise and process variations. Digital PLLs allow faster lock time and are used for clock generation in high performance microprocessors. A digital PLL has more advantages as compared to an analog PLL. Digital PLLs are more flexible in terms of calibration, programability, stability and they are more immune to noise. The cost of a digital PLL is less as compared to its analog counter part. Digital PLLs are analogous to the analog PLLs, but the components used for implementing a digital PLL are digital. A digitally controlled oscillator (DCO) is utilized instead of a voltage controlled oscillator. A time to digital converter(TDC) is used instead of the phase frequency detector. The analog filter is replaced with a digital low pass filter. Phase-locked loop is a very good research topic in electronics. It covers many topics in the electrical systems such as communication theory, control systems and noise characterization. This project work describes the design and simulation of miscellaneous blocks of an all-digital PLL for the 60 GHz band. The reference frequency is 54 MHz and the DCO output frequency is 2 GHz to 3 GHz in a state-of the-art 65 nm process, with 1 V supply voltage. An all-digital PLL is composed of digital components such as a low pass filter, a sigma delta modulator and a fractional N /N +1 divider for low voltage and high speed operation. The all-digital PLL is implemented in MATLAB and then the filter, a sigma delta modulator and a fractional N /N +1 divider are implemented in MATLAB and Verilog-A code. The sub blocks i.e full adder, D flip-flop, a digital to digital converter, a main counter, a prescalar and a swallow counter are implemented in the transistor level using CMOS 65nm technology and functionality of each block is verified.

An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the important block in all-digital phase locked loop. Several time-to-digital converter architectures were studied and simulated. TheVernier delay based architecture and inverter delay based architecture was designedand evaluated. There architectures provided certain short comings whilethe pseudo-differential time-to-digital converter architecture was chosen, becauseof it’s less occupation of area. Since there exists a relationship between the sizeof the delay cells and it’s time resolution, the pseudo-differential time-to-digitalconverter severed it’s purpose. The whole time-to-digital converter system was tested on a 1 V power supply,reference frequency 54-MHz which is also the reference clock Fref , and a feedbackfrequency Fckv 2.1-GHz. The power consumption was found to be around 2.78mW without dynamic clock gating. When the clock gating or bypassing is done,the power consumption is expected to be reduced considerably. The measuredtime-to-digital converter resolution is around 7 ps to 9 ps with a load variation of15 fF. The inherent delay was also found to be 5 ps. The total output noise powerwas found to be -128 dBm.

Time to digital converter (TDC) is a digital unit that measures the time interval between two events.This is useful to determine the characteristics and patterns of a signal or an event. In this thesis ahybrid TDC is presented consisting of a tapped delay line and a clock counter principle. The TDC is used to measure the time between received data in a QKD application. If the measuredtime does not exceed a certain value then data had been sent without any interception. It is alsopossible to use TDCs in other fields such as laser-ranging and time-of-flight applications. The TDC consists of two carry chains, an encoder, a FIFO and a counter for each channel, anAXI-module and a control unit to generate command signals to all channels that are implemented.The time is measured by sampling the signal that has propagated through the carry chain and from thissample encode the propagation length. In this thesis a TDC is implemented that has a 10 ns dead time and a resolution below 28 psin a four channel mode. The propagation variation is approximately two percent of the total valueduring testing. For the implementation an FPGA-board with a Zynq XC7Z020 SoC is used withSystemVerilog that is a hardware describing language (HDL).

Since 2001 the top international Notebook PC brand firm, Dell, established their Research and Development Center (R&D Center), or called TDC (Taiwan Design Center), in Taiwan, other Notebook PC firms also set up R&D Centers in Taiwan to work closely with Taiwan Notebook PC ODMs. In 2006, Dell has already handed over all the consumer Notebook R&D teams to TDC in Taiwan. Hewlett-Packard (HP) established R&D center in Taiwan in 2002, it is called Product Development Center (PDC) and now has thousands of engineers. The major responsibility of R&D Centers in Taiwan is to cooperate with Notebook PC ODMs to develop and manufacture Notebook PCs. The purpose of this study is to understand how the R&D Center evaluates Notebook PC ODMs and what the key factors are for evaluation from the R&D perspective. This study is taken by the depth of literature review and expert interviews and used AHP to develop a model of the evaluation to select a Notebook PC ODM as the partner to develop a new Notebook PC and mass-produce the products after complete development and validation. On the other hand, it helps Notebook PC ODMs to understand the client's selection criteria and know what the weaknesses are to improve accordingly.

Rapid scaling in technology has introduced new challenges in the realm of traditional analog design. Scaling of supply voltage directly impacts the available voltage-dynamic-range. On the other hand, nanometric technologies with fT in the hundreds of GHz range open opportunities for time-resolution-based signal processing. With reduced available voltage-dynamic-range and improved timing resolution, it is more convenient to devise analog circuits whose performance depends on edge-timing precision rather than voltage levels. Thus, instead of representing the data/information in the voltage-mode, as a difference between two node voltages, it should be represented in time-mode as a time-difference between two rising and/or falling edges. This dissertation addresses the feasibility of employing time-mode analog circuit design in different applications. Specifically: 1) Time-mode-based quanitzer and feedback DAC of SigmaDelta ADC. 2) Time-mode-based low-THD 10MHz oscillator, 3) A Spur-Frequency Boosting PLL with -74dBc Reference-Spur Rejection in 90nm Digital CMOS. In the first project, a new architectural solution is proposed to replace the DAC and the quantizer by a Time-to-Digital converter. The architecture has been fabricated in 65nm and shows that this technology node is capable of achieving a time-matching of 800fs which has never been reported. In addition, a competitive figure-of-merit is achieved. In the low-THD oscillator, I proposed a new architectural solution for synthesizing a highly-linear sinusoidal signal using a novel harmonic rejection approach. The chip is fabricated in 130nm technology and shows an outstanding performance compared to the state of the art. The designed consumes 80% less power; consumes less area; provides much higher amplitude while being composed of purely digital circuits and passive elements. Last but not least, the spur-frequency boosting PLL employs a novel technique that eliminates the reference spurs. Instead of adding additional filtering at the reference frequency, the spur frequency is boosted to higher frequency which is, naturally, has higher filtering effects. The prototype is fabricated in 90nm digital CMOS and proved to provide the lowest normalized reference spurs ever reported.

High-speed serial links in modern communication systems often require the Bit-Error-Rate (BER) to be at the level of 10 −12 or lower. From the industry perspective, major drawbacks in high volume production test for the serial links with low BER are the excessive test time for comparing each captured bit for error detection and costly instrumentation. In this thesis, we focus on developing a novel BER estimation methodology and its implementation. We propose a novel BER estimation methodology and an effective self-test system, which not only eliminates the usage of expensive measuring instruments, but also significantly reduces the test time. In the proposed BER estimation, we show that the total jitter (TJ) spectral information of a test SerDes is successfully estimated from the known TJ distribution of a golden SerDes. We propose a novel BER estimation formula that incorporates not only the TJ spectral information of the serial data, but also the TJ spectral information of the recovered clock. Our proposed estimation formula enables efficient BER estimation without excessive test time, and its accuracy does not depend on the jitter present in the serial data stream of the SerDes. The experimental results demonstrate that the test time for the proposed BER estimation is in the order of seconds, which translates to the test time savings of more than hundred times compared to the traditional BER measurement for the same accuracy. To implement the proposed BER estimation methodology, we have developed a novel time-to-digital converter (TDC). This design effectively measures the delay between two signals and converts it into the digital format. Performance of the TDC has been evaluated and presented using ModelSim and SPICE simulation. / Electrical and Computer Engineering

Le déploiement à grande échelle de l’internet des objets nécessite le développement de systèmes de radiocommunication plus économes en énergie, dont le circuit de génération de fréquences est connu pour être particulièrement énergivore. L’objectif de ce travail de thèse est donc d’une part de développer une synthèse de fréquences très faible consommation et d’autre part de démontrer les performances de la technologie FDSOI pour des applications analogiques et radiofréquences. Dans le premier chapitre sont présentées les spécifications du standard choisi -le BLE-, les spécificités de la technologie FDSOI et l'état de l’art des architectures de transmetteurs radiofréquences à faible consommation. Nous avons retenue de cette comparaison l'architecture à division par phases. Le deuxième chapitre présente les résultats de trois types de modélisation système de l’architecture ; 1 - le fonctionnement de ses composants et les points clés à respecter pour son implémentation, 2 - le comportement en bruit de phase pour la définition des spécifications, et 3 - l’impact de l’architecture sur la génération de raies spectrales parasites. Cette étude nous a permis de fixer le cahier des charges du VCRO développé au chapitre suivant. Le troisième chapitre est consacré à la conception, la réalisation et le test de 4 topologies de VCROs en technologie FDSOI 28nm et d'un circuit de test. Les premiers résultats de mesure sont encourageants mais nécessitent d’être complétés par des mesures avec PLL fractionnaire intégrée. En effet, la sensibilité des circuits à la tension d’alimentation (pushing de l’ordre de 5 GHz/V) a rendu les mesures du bruit de phase très délicates. / The large-scale deployment of IoT requires the development of more efficient energy radio systems, within which the frequency generation circuit is known to be particularly energy-consuming. The objective of this thesis is firstly to develop a very low consumption frequency synthesis and secondly to demonstrate the performance of the FDSOI technology for analog and RF applications.In the first chapter are the specifications of the chosen standard -the BLE-, the specifications of the FDSOI technology and state of the art of low power radio frequency synthesizers architecture. We have chosen from this comparison the Fractional Phase Divider architecture. The second chapter presents the results of three types of system simulations of the PLL; 1 - the operation of its components and the key points to be respected for its implementation, 2 - the phase noise behavior for the definition of specifications, and 3 - the impact of architecture on the generation of spurious. This study allowed us to set the specifications of VCROs developed in the next chapter. The third chapter is dedicated to the design, implementation and testing of four topologies of VCROs and a test circuit in FDSOI 28nm technology. The first measurement results are encouraging but they need to be complemented by an integrated fractional PLL measurement. Indeed, the sensitivity of the circuits to the supply voltage (pushing of about 5 GHz/V) made measurements of phase noise very delicate. The measured consumption is less than 0.8 mA and the surface of the circuits is of the order of 600 µm².In the fourth and final chapter we present the implementation at circuit-level of a phase synchronization PLL.

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O objetivo deste estudo foi analisar como o desempenho motor de crianças com Transtorno do Déficit de Atenção e Hiperatividade (TDAH) pode ser afetado pela coocorrência do Transtorno do Desenvolvimento da Coordenação (TDC). Embora a relação entre ambos os transtornos tenha sido reconhecida há vários anos, alguns aspectos relativos a essa associação permanecem incertos. Alguns estudos têm atribuído as falhas na competência motora à distração e à impulsividade, enquanto outros têm referido as dificuldades motoras no TDAH, como uma consequência da comorbidade com o TDC. Método: Inicialmente, 283 crianças com idade entre seis e dez anos participaram deste estudo. Após uma etapa de rastreio dos sintomas de TDAH pelo questionário SNAP-IV, respondido pelos pais e professores, e pela avaliação por meio da Movement Battery Assessment for Children, segunda edição, 27 crianças foram então divididas em dois grupos, TDAH (14) e TDAH/TDC (13). A Escala de Desenvolvimento Motor foi utilizada para avaliar a motricidade global e fina, equilíbrio, esquema corporal, organização espacial e temporal. Resultados: Ambos os grupos demonstraram risco para atraso no desenvolvimento. Os testes revelaram diferenças estatisticamente significativas entre os grupos TDAH e TDAH/TDC nos quocientes motores de motricidade fina (p = 0,04) e equilíbrio (p = 0,02). Discussão: O presente estudo reforça que o TDAH pode apresentar dificuldades motoras, mesmo quando o TDC não está coocorrendo. Os resultados também sugerem dificuldades específicas de motricidade fina e equilíbrio para aqueles com TDAH e TDC. Esses achados podem aumentar a compreensão desta relação e esclarecer quais problemas são intrínsecos ao TDAH e como a coocorrência de TDC pode afetar o desempenho motor destas crianças / The aim of this study was to analyze how the motor performance of children with Attention Deficit Hyperactivity Disorder (ADHD) may be affected by the co-occurrence with Developmental Coordination Disorder (DCD). Although the relationship between both disorders has been recognized for several years, some aspects regarding its association remain unclear. Some studies have attributed the lack of motor competence to distractibility and impulsiveness, and others have associated the motor difficulties in ADHD as a consequence of the comorbidity with DCD. Method: Initially, 283 children aged six to ten years participated in this study. After being screened by SNAP-IV parent and teacher rating scale and the Movement Assessment Battery for Children second edition, 27 children were then divided in two groups, ADHD (14) and ADHD/DCD (13). Motor Development Scale was used to assess global and fine motricity, balance, body scheme, and spatial and temporal organization. Results: Both groups demonstrated a risk for delayed development. Between-group testing revealed statistically significant differences between the ADHD and ADHD/DCD groups for fine motricity (p=0.04) and balance (p=0.02) motor quotients. Discussion: The current study reinforces that ADHD may have motor difficulties, even when DCD is not co-occurring. The results also suggested particular difficulties in fine motricity and balance for those with ADHD and DCD. These findings may increase the understanding of this relationship and clarify what problems are intrinsic to ADHD and how the co-occurrence of DCD may affect the motor performance in these children

O objetivo deste estudo foi analisar como o desempenho motor de crianças com Transtorno do Déficit de Atenção e Hiperatividade (TDAH) pode ser afetado pela coocorrência do Transtorno do Desenvolvimento da Coordenação (TDC). Embora a relação entre ambos os transtornos tenha sido reconhecida há vários anos, alguns aspectos relativos a essa associação permanecem incertos. Alguns estudos têm atribuído as falhas na competência motora à distração e à impulsividade, enquanto outros têm referido as dificuldades motoras no TDAH, como uma consequência da comorbidade com o TDC. Método: Inicialmente, 283 crianças com idade entre seis e dez anos participaram deste estudo. Após uma etapa de rastreio dos sintomas de TDAH pelo questionário SNAP-IV, respondido pelos pais e professores, e pela avaliação por meio da Movement Battery Assessment for Children, segunda edição, 27 crianças foram então divididas em dois grupos, TDAH (14) e TDAH/TDC (13). A Escala de Desenvolvimento Motor foi utilizada para avaliar a motricidade global e fina, equilíbrio, esquema corporal, organização espacial e temporal. Resultados: Ambos os grupos demonstraram risco para atraso no desenvolvimento. Os testes revelaram diferenças estatisticamente significativas entre os grupos TDAH e TDAH/TDC nos quocientes motores de motricidade fina (p = 0,04) e equilíbrio (p = 0,02). Discussão: O presente estudo reforça que o TDAH pode apresentar dificuldades motoras, mesmo quando o TDC não está coocorrendo. Os resultados também sugerem dificuldades específicas de motricidade fina e equilíbrio para aqueles com TDAH e TDC. Esses achados podem aumentar a compreensão desta relação e esclarecer quais problemas são intrínsecos ao TDAH e como a coocorrência de TDC pode afetar o desempenho motor destas crianças / The aim of this study was to analyze how the motor performance of children with Attention Deficit Hyperactivity Disorder (ADHD) may be affected by the co-occurrence with Developmental Coordination Disorder (DCD). Although the relationship between both disorders has been recognized for several years, some aspects regarding its association remain unclear. Some studies have attributed the lack of motor competence to distractibility and impulsiveness, and others have associated the motor difficulties in ADHD as a consequence of the comorbidity with DCD. Method: Initially, 283 children aged six to ten years participated in this study. After being screened by SNAP-IV parent and teacher rating scale and the Movement Assessment Battery for Children second edition, 27 children were then divided in two groups, ADHD (14) and ADHD/DCD (13). Motor Development Scale was used to assess global and fine motricity, balance, body scheme, and spatial and temporal organization. Results: Both groups demonstrated a risk for delayed development. Between-group testing revealed statistically significant differences between the ADHD and ADHD/DCD groups for fine motricity (p=0.04) and balance (p=0.02) motor quotients. Discussion: The current study reinforces that ADHD may have motor difficulties, even when DCD is not co-occurring. The results also suggested particular difficulties in fine motricity and balance for those with ADHD and DCD. These findings may increase the understanding of this relationship and clarify what problems are intrinsic to ADHD and how the co-occurrence of DCD may affect the motor performance in these children