Le Groupe de recherche en appareillage médical de Sherbrooke possède une expertise unique dans la conception de scanners à tomographie d’émission par positrons. Le fonctionnement de la tomographie d’émission par positrons repose sur la détection de photons d’annihilation colinéaires par un agencement de cristaux scintillateurs, photodétecteurs, convertisseurs temps-numérique et électronique de traitement. Une partie du groupe de recherche s’oriente vers l’utilisation des matrices de photodiodes à avalanches opérées en mode Geiger, afin d’obtenir une meilleure résolution temporelle du système et un seuil de détection plus faible que les générations précédentes,ce qui permet de détecter les premiers photons émis par le cristal scintillateur. Le convertisseur temps-numérique (TDC) développé se veut un bloc polyvalent et réutilisable mesurant des intervalles de temps avec grande précision. Son développement cible des applications de détection monophotoniques avec estampilles temporelles comme la tomographie optique dffuse, les caméras 3D ou la tomographie d’émission par positrons. Il s’intègre ici dans un circuit intégré en CMOS 130 nm assemblé verticalement avec plusieurs gaufres et dédié à la détection en tomographie d’émission par positron. La méthodologie de conception du convertisseur temps-numérique s’inspire d’une approche en signaux mixtes avec suprématie du numérique. En simulation, le TDC développé arbore une résolution de 14,5 ps, une non-linéarité différentielle de 1 bits de poids faible, une non-linéarité intégrale de 2,2 bits de poids faible, une fréquence de conversion de 11,1 millions d’échantillons par seconde, une plage dynamique de 5 ns, une puissance moyenne consommée en moyenne de 4,5 mW et une taille de 0,029 mm². Un mécanisme pour améliorer la résolution du TDC a été intégré dans un exemplaire du TDC. Son utilisation a permis d’obtenir une résolution de 12,6 ps sur un exemplaire du circuit fabriqué. Ces travaux ont permis d’explorer l’architecture en oscillateur vernier avec anneaux et d’en faire ressortir plus clairement les avantages, les inconvénients et les écueils à surveiller lors de la conception.

The pavement system is subjected to complex stress states under vehicular loading. A combination of axial and shear stress has been identified as a potential cause of top down cracking (or more precisely near surface cracking) in asphalt surface. Therefore, in terms of modeling the material response a pertinent question is whether the typical one-dimensional viscoelastic properties of the material are affected by a multi-axial stress state. Such changes are referred to as interaction non-linearity. The objective of this study was to evaluate whether or not asphalt composites are susceptible to such interaction effects. The study was conducted using fine aggregate matrix (FAM), which comprises graded sand and asphalt binder. To provide multi-modal loading, the rectangular prismatic FAM specimens were used with the Arcan apparatus. This apparatus ensures low bending stress and offers adjustments in the setup to provide different proportions of axial and shear stress. Finite element modeling was done to evaluate the stress state for different orientations of the sample in the Arcan apparatus. For measurement of strain, the study used digital image correlation (DIC), which is an optical, non-contact measurement technology. The strain thus measured was used to compute shear compliance. Fitting parameters of the shear compliances were estimated for power-law and Prony series for different loading orientations. When compared, the measured shear compliances do not show perceivable variation with respect to different proportion of axial stress applied in conjunction. However, further testing with different temperatures and other magnitudes of shear stress is necessary. This study is the first step to allow modeling of stress and crack propagation behavior near the pavement surface where complex stress state is present. / text

This bachelor thesis has been performed at Saab Dynamics AB in Karlskoga, with the purpose to design simulation models and analyze the technology study for distance measurement based on Time Of Flight (TOF) -principle. The distance measurement is implemented by short laser pulses and Time-to-Digital Converter (TDC). This method uses the time difference between when the laser pulse is transmitted to the time when its reflection from an object returns to the detector. With this technology as a starting point for this thesis, an analysis has been made by looking at the subsystems when it gets affected by different parameters. The simulation will give an expected result which has been compared with the measurement results. On this basis a ranking of the parameters according by the influence of the functionality has been delivered. / Det här examensarbetet har utförts vid Saab Dynamics AB i Karlskoga med syftet att modellera och analysera en teknikstudie för avståndsmätning baserad på Time-Of-Flight-principen (TOF-principen). Avståndsmätningen genomförs med korta laserpulser och Time-to-Digital Converter (TDC). Det är en metod för avståndsmätning som baseras på tidsskillnaden från den tidpunkt då laserpulsen skickas från laserdioden till den tidpunkt då fotodioden har detekterat den reflekterade laserpulsen. Med den nya teknikstudien som utgångspunkt för arbetet har en analys på hur avståndsmätarens delsystem påverkats av olika parametrar genomförts där förväntat resultat har jämförts med mätresultat. Med detta som grund har en rangordning av parametrarna efter hur stor inverkan de har på funktionaliteten levererats.

Ce travail porte sur la mise en oeuvre en 3d de la méthode des éléments naturels contrainte CNEM en vue de son utilisation pour la simulation du cisaillage à grande vitesse. La CNEM est une approche à mi-chemin des approches sans maillage et des éléments finis. La construction de son interpolation utilise le diagramme de Voronoï contraint (dual du maillage de Delaunay contraint) associé à un nuage de noeud réparti sur le domaine étudié muni d'une description de sa frontière. La mise en oeuvre de la CNEM comporte trois aspects principaux : i) la construction du diagramme de Voronoï contraint, ii) le calcul des fonctions de forme éléments naturels Sibson, iii) la discrétisation d'une formulation variationnelle générique par utilisation de l'intégration nodale stabilisée conforme, SCNI, introduite par Chen et Al en 2001. Une partie importante de ce travail concerne les deux derniers points. Pour le calcul des fonctions de formes Sibson 3d cinq algorithmes sont présentés, dont deux développés au cours de la thèse, et sont comparés en terme de performance. Par ailleurs, une discrétisation est proposée pour être applicable au cas des domaines fortement non convexes. La mise en oeuvre proposée est validée sur des exemples en élasticité linéaire 3d en petites perturbations (vis à vis de solutions analytiques et de résultats éléments finis) puis en grandes transformations (test de la barre de Taylor). L'application de la CNEM au cisaillage grande vitesse est finalement abordée. Les développements effectués ont été intégrés à la plateforme logicielle Nessy. Cette plateforme a pour objectif la capitalisation du savoir faire du LMSP en simulation numérique.

The demand for cooling and air-conditioning of building is increasingly ever growing. This increase is mostly due to population and economic growth in developing countries, and also desire for a higher quality of thermal comfort. Increase in the use of conventional cooling systems results in larger carbon footprint and more greenhouse gases considering their higher electricity consumption, and it occasionally creates peaks in electricity demand from power supply grid. Solar energy as a renewable energy source is an alternative to drive the cooling machines since the cooling load is generally high when solar radiation is high. This thesis examines the performance of PV/T solar collector manufactured by Solarus company in a solar cooling system for an office building in Dubai, New Delhi, Los Angeles and Cape Town. The study is carried out by analyzing climate data and the requirements for thermal comfort in office buildings. Cooling systems strongly depend on weather conditions and local climate. Cooling load of buildings depend on many parameters such as ambient temperature, indoor comfort temperature, solar gain to the building and internal gains including; number of occupant and electrical devices. The simulations were carried out by selecting a suitable thermally driven chiller and modeling it with PV/T solar collector in Polysun software. Fractional primary energy saving and solar fraction were introduced as key figures of the project to evaluate the performance of cooling system. Several parametric studies and simulations were determined according to PV/T aperture area and hot water storage tank volume. The fractional primary energy saving analysis revealed that thermally driven chillers, particularly adsorption chillers are not suitable to be utilizing in small size of solar cooling systems in hot and tropic climates such as Dubai and New Delhi. Adsorption chillers require more thermal energy to meet the cooling load in hot and dry climates. The adsorption chillers operate in their full capacity and in higher coefficient of performance when they run in a moderate climate since they can properly reject the exhaust heat. The simulation results also indicated that PV/T solar collector have higher efficiency in warmer climates, however it requires a larger size of PV/T collectors to supply the thermally driven chillers for providing cooling in hot climates. Therefore using an electrical chiller as backup gives much better results in terms of primary energy savings, since PV/T electrical production also can be used for backup electrical chiller in a net metering mechanism.

Abstract The aim of this work was to improve the performance and usability of a digital time-to-digital converter (TDC) in CMOS technology. The characteristics of the TDC were improved especially for the needs of pulsed laser time-of-flight (TOF) distance measurement, where picosecond-level precision with a long µs-level measurement range is needed in order to approach mm-level measurement accuracy. Stability in the face of process, voltage and temperature variations, multiple measurement channels, alternative measurement modes, a high integration level, standard interfaces and simple usage were the main features for development. The measurement architecture is based on counter and timing signal interpolation on two levels. The counter counts the full reference clock cycles between the timing signals, while a new recycling delay line developed in this thesis interpolates within the reference clock cycle. This technique utilizes a short delay line several times per reference clock cycle, which minimizes the interpolation nonlinearity. The same structure also makes the use of a low, MHz-level reference frequency possible, and thus only a crystal is needed as an external oscillator component. The parallel load capacitor-scaled delay line structure acts as the second, sub-gate-delay interpolation level. The INL does not accumulate in elements connected in parallel, and the load capacitance differences enable high, ps-level resolution to be achieved. Four TDC circuits in 0.35 µm CMOS technology were designed and tested in the course of this work, of which the latest, a 7-channel TDC, is able to measure the time intervals between the start pulse and three separate stop pulses in one measurement and to resolve the pulse widths or rise times at the same time. In laser TOF distance measurement this functionality can be used when several echoes arrive at the receiver, and also to compensate for the detection threshold problem known as timing walk error. The TDC achieves 8.9 ps interpolation resolution within the cycle time of a 20 MHz reference clock using only 8 delay elements on the first interpolation level and 14 delay elements on the second. A measurement precision better than 9 ps was achieved without using result post-processing or look-up tables. This work shows that versatile, high performance TDCs can be created in standard CMOS technology. / Tiivistelmä Väitöskirjatyön tavoitteena oli parantaa CMOS-aika-digitaalimuuntimien suorituskykyä ja käytettävyyttä. Muuntimen ominaisuuksia kehitettiin erityisesti laseretäisyysmittauksen tarpeita ajatellen, missä millimetritason mittaustarkkuus laajalla mittausaluella edellyttää aika-digitaalimuuntimelta pikosekuntitason tarkkuutta mikrosekuntien mittausalueella. Stabiilius prosessiparametri-, jännite- ja lämpötilavaihteluita vastaan, useat mittauskanavat, useat mittausmoodit, korkea integraatioaste, standardoidut liitäntäväylät ja helppo käytettävyys olivat erityisesti kehityksen kohteina. Suunniteltu mittausarkkitehtuuri koostuu laskurista ja kaksitasoisesta ajoitussignaali-interpolaattorista. Laskuri laskee kokonaiset referenssikellojaksot ajoitussignaalien välillä ja työssä kehitetty referenssiä kierrättävä viivelinjarakenne rekistereineen interpoloi ajoitussignaalien paikat referenssikellojaksojen sisältä. Referenssinkierrätystekniikka hyödyntää lyhyttä viivelinjaa useampaan kertaan kellojakson aikana, mikä minimoi epälineaarisuuden interpoloinnissa. Sama rakenne mahdollistaa myös MHz-tason referenssitaajuuden, jolloin matalataajuista kidettä voidaan käyttää referenssilähteenä. Toinen interpolointitaso koostuu rinnakkaisista kapasitanssiskaalatuista viive-elementeistä, mitkä mahdollistavat alle porttiviiveen mittausresoluution. Rinnakkaisessa rakenteessa elementtien epälineaarisuudet eivät summaudu, mikä mahdollistaa pikosekuntitason mittaustarkkuuden. Väitöskirjatyössä suunniteltiin ja toteutettiin neljä aikavälinmittauspiiriä käyttäen 0,35 µm CMOS-teknologiaa, joista viimeisin, 7-kanavainen muunnin kykenee mittaamaan aikavälin useampaan pulssiin yhdellä kertaa sekä voi selvittää samalla pulssien leveydet tai nousuajat. Laseretäisyysmittauksessa monikanavaisuutta voidaan käyttää kun useita kaikuja lähetetystä pulssista saapuu vastaanottimeen sekä kompensoimaan mittauksessa esiintyviä muita virhelähteitä. Käytettäessä 20 MHz:n kidettä referenssilähteenä muunnin saavuttaa alle 9 ps:n interpolointiresoluution ja tarkkuuden ilman epälineaarisuudenkorjaustaulukoita. Työ osoittaa, että edullisella CMOS-teknologialla voidaan toteuttaa monipuolinen ja erittäin suorituskykyinen aika-digitaalimuunnin.

This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442μW with 1.2V power supply. Measured integral nonlinearity and differential nonlinearity are 0.5LSB and 0.33LSB respectively.

No description available.

Vision has always been one of the most important cognitive tools of human beings. In this regard, the development of image sensors opens up the potential to view objects that our eyes cannot see. One of the most promising capability in some image sensors is their single-photon sensitivity that provides information at the ultimate fundamental limit of light. Time-resolved single-photon avalanche diode (SPAD) image sensors bring a new dimension as they measure the arrival time of incident photons with a precision in the order of hundred picoseconds. In addition to this characteristic, they can be fabricated in complementary metal-oxide-semiconductor (CMOS) technology enabling the integration of complex signal processing blocks at the pixel level. These unique features made CMOS SPAD sensors a prime candidate for a broad spectrum of applications. This thesis is dedicated to the optimization and characterization of quantum imagers based on the SPADs as part of the E.U. funded SUPERTWIN project to surpass the fundamental diffraction limit known as the Rayleigh limit by exploiting the spatio-temporal correlation of entangled photons. The first characterized sensor is a 32×32-pixel SPAD array, named “SuperEllen”, with in-pixel time-to-digital converters (TDC) that measure the spatial cross-correlation functions of a flux of entangled photons. Each pixel features 19.48% fill-factor (FF) in 44.64-μm pitch fabricated in a 150-nm CMOS standard technology. The sensor is fully characterized in several electro-optical experiments, in order to be used in quantum imaging measurements. Moreover, the chip is calibrated in terms of coincidence detection achieving the minimal coincidence window determined by the SPAD jitter. The second developed sensor in the context of SUPERTWIN project is a 224×272-pixel SPAD-based array called “SuperAlice”, a multi-functional image sensor fabricated in a 110-nm CMOS image sensor technology. SuperAlice can operate in multiple modes (time-resolving or photon counting or binary imaging mode). Thanks to the digital intrinsic nature of SPAD imagers, they have an inherent capability to achieve a high frame rate. However, running at high frame rate means high I/O power consumption and thus inefficient handling of the generated data, as SPAD arrays are employed for low light applications in which data are very sparse over time and space. Here, we present three zero-suppression mechanisms to increase the frame rate without adversely affecting power consumption. A row-skipping mechanism that is implemented in both SuperEllen and SuperAlice detects the absence of SPAD activity in a row to increase the duty cycle. A current-based mechanism implemented in SuperEllen ignores reading out a full frame when the number of triggered pixels is less than a user-defined value. A different zero-suppression technique is developed in the SuperAlice chip that is based on jumping through the non-zero pixels within one row. The acquisition of TDC-based SPAD imagers can be speeded up further by storing and processing events inside the chip without the need to read out all data. An on-chip histogramming architecture based on analog counters is developed in a 150-nm CMOS standard technology. The test structure is a 16-bin histogram with 9 bit depth for each bin. SPAD technology demonstrates its capability in other applications such as automotive that demands high dynamic range (HDR) imaging. We proposed two methods based on processing photon arrival times to create HDR images. The proposed methods are validated experimentally with SuperEllen obtaining >130 dB dynamic range within 30 ms of integration time and can be further extended by using a timestamping mechanism with a higher resolution.

First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is presented and through the analysis and measurement results of this synthesizer, the need for low power circuit techniques in frequency dividers is discussed. Next, Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cells are explored for implementing radio-frequency (RF) frequency dividers of low power frequency synthesizers. DCVSL ip- ops offer small input and clock capacitance which makes the power consumption of these circuits and their driving stages, very low. We perform a delay analysis of DCVSL circuits and propose a closed-form delay model that predicts the speed of DCVSL circuits with 8 percent worst case accuracy. The proposed delay model also demonstrates that DCVSL circuits suffer from a large low-to-high propagation delay ( PLH) which limits their speed and results in asymmetrical output waveforms. Our proposed enhanced DCVSL, which we call DCVSL-R, solves this delay bottleneck, reducing PLH and achieving faster operation. We implement two ring-oscillator-based voltage controlled oscillators (VCOs) in 0.13 mu m technology with DCVSL and DCVSL-R delay cells. In measurements, for the same oscillation frequency (2.4GHz) and same phase noise (-113dBc/Hz at 10MHz), DCVSL-R VCO consumes 30 percent less power than the DCVSL VCO. We also use the proposed DCVSL-R circuit to implement the 2.4GHz dual-modulus prescaler of a low power frequency synthesizer in 0.18 mu m technology. In measurements, the synthesizer exhibits -135dBc/Hz phase noise at 10MHz offset and 58 mu m settling time with 8.3mW power consumption, only 1.07mWof which is consumed by the dual modulus prescaler and the buffer that drives it. When compared to other dual modulus prescalers with similar division ratios and operating frequencies in literature, DCVSL-R dual modulus prescaler demonstrates the lowest power consumption. An all digital phase locked loop (ADPLL) that operates for a wide range of frequencies to serve as a multi-protocol compatible PLL for microprocessor and serial link applications, is presented. The proposed ADPLL is truly digital and is implemented in a standard complementary metal-oxide-semiconductor (CMOS) technology without any analog/RF or non-scalable components. It addresses the challenges that come along with continuous wide range of operation such as stability and phase frequency detection for a large frequency error range. A proposed multi-bit bidirectional smart shifter serves as the digitally controlled oscillator (DCO) control and tunes the DCO frequency by turning on/off inverter units in a large row/column matrix that constitute the ring oscillator. The smart shifter block is completely digital, consisting of standard cell logic gates, and is capable of tracking the row/column unit availability of the DCO and shifting multiple bits per single update cycle. This enables fast frequency acquisition times without necessitating dual loop fi lter or gear shifting mechanisms. The proposed ADPLL loop architecture does not employ costly, cumbersome DACs or binary to thermometer converters and minimizes loop filter and DCO control complexity. The wide range ADPLL is implemented in 90nm digital CMOS technology and has a 9-bit TDC, the output of which is processed by a 10-bit digital loop filter and a 5-bit smart shifter. In measurements, the synthesizer achieves 2.5GHz-7.3GHz operation while consuming 10mW/GHz power, with an active area of 0.23 mm2.