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International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / In this paper, a PCM telemetry system based on Personal computer is presented and some important methods that are used to realize the system will be introduced, such as a new kind of all digital PLL bit synchronizer and a way to solve the problem of high-rate data storage. The main idea of ours is to make the basic parts of PCM telemetry system (except receiver) in the form of PC cards compatible with EISA Bus, which forms a telemetry station with resource of PC computer. Finally, a laboratory prototype with rate up to 3.2Mbps is built.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / This paper discusses the design and performance of the FM/PM/BPSK "personal computer card-based" receiver. In PSK, a carrier recovery technique must be used for signal demodulation. Costas loop is a well known method and is the basis in the design of the BPSK demodulation. A new design approach employing digital Box Car arm filters is used to improve receiver performance and flexibility. Detail design and performance of the digital Costas loop will be explored in a later section. A classical technique is employed for Phase demodulation with the use of tracking Phase Lock Loop. Frequency demodulation is designed around a simple, single FM discriminator IC.

The work was based on digitally controlled oscillator for an all-digital PLL in 65nm process. Phase locked loop’s were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existinggeneration, there has to be quick development with the technique. In such case ananalog PLL which was used earlier gradually getting converted to digital circuit.All-digital PLL blocks does the same work as an analog PLL blocks, but thecircuits and other control circuitry designed were completely in digital form, becausedigital circuit has many advantages over analog counterpart when they arecompared with each other. Digital circuit could be scaled down or scaled up evenafter the circuits were designed. It could be designed for low power supply voltageand easy to construct in a 65 nm process. The digital circuit was widely chosento make life easier. In most of the application PLL’s were used for clock and data recovery purpose,from that perspective jitter will stand as a huge problem for the designers. Themain aim of this thesis was to design a DCO that should bring down the jitter asdown as possible which was designed as standalone, the designed DCO would belater placed in an all-digital PLL. To understand the concept and problem aboutjitter at the early stage of the project, an analog PLL was designed in block leveland tested for different types of jitter and then design of a DCO was started. This document was about the design of a digitally controlled oscillator whichoperates with the center frequency of 2.145 GHz. In the first stage of the projectthe LC tank with NMOS structure was built and tested. In the latter stage the LCtank was optimized by using PMOS structure as negative resistance and eventuallyended up with NMOS and PMOS cross coupled structure. Tuning banks were oneof the main design in this project which plays a key role in locking the system ifthe DCO is placed in an all-digital PLL system. So, three types of tuning bankswere introduced to make the system lock more precisely. The control circuits andthe varactors built were all digital and hence it is called as digitally controlledoscillator. Digital control circuits, other sub-blocks like differential to single endedand simple buffers were also designed to optimize the signal and the results wereshown.DCO and tuning banks were tested using different types of simulation and were tested for different jitter qualities and analysis. The simulation results are shownin the final chapter simulation and results.

The main scope of this thesis is to implement a new architecture of a high bandwidth phase-locked loop (PLL) with a large operating frequency range from 100~MHz to 1~GHz in a 150~$nm$ CMOS process. As PLL is the time-discrete system, the new architecture is mathematically modelled in the z-domain. The charge pump provides a proportionally damped signal, which is unlikely as a resistive or capacitive damping used in the conventional charge pump. The new damping results in a less update jitter and less peaking to achieve the lock frequency and fast locking time of the PLL. The new semi-digital PLL architecture uses $N$ storage cells. The $N$ storage cells is used to store the oscillator tuning information digitally and also enables analogue tuning of the voltage controlled oscillator (VCO). The storage cells outputs are also used for the process voltage temperature compensation. The phase-frequency detector (PFD) and VCO are implemented like a conventional PLL. The bandwidth achieved is 1/4th of the PFD update frequency for all over the operating range from 100~MHz to 1~GHz. The simulation results are also verified with the mathematical modelling. The new architecture also consumes less power and area compared to the conventional PLL.

abstract: Phase locked loops are an integral part of any electronic system that requires a clock signal and find use in a broad range of applications such as clock and data recovery circuits for high speed serial I/O and frequency synthesizers for RF transceivers and ADCs. Traditionally, PLLs have been primarily analog in nature and since the development of the charge pump PLL, they have almost exclusively been analog. Recently, however, much research has been focused on ADPLLs because of their scalability, flexibility and higher noise immunity. This research investigates some of the latest all-digital PLL architectures and discusses the qualities and tradeoffs of each. A highly flexible and scalable all-digital PLL based frequency synthesizer is implemented in 180 nm CMOS process. This implementation makes use of a binary phase detector, also commonly called a bang-bang phase detector, which has potential of use in high-speed, sub-micron processes due to the simplicity of the phase detector which can be implemented with a simple D flip flop. Due to the nonlinearity introduced by the phase detector, there are certain performance limitations. This architecture incorporates a separate frequency control loop which can alleviate some of these limitations, such as lock range and acquisition time. / Dissertation/Thesis / M.S. Electrical Engineering 2012

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First, a frequency synthesizer for IEEE 802.15.4 / ZigBee transceiver applications that employs dynamic True Single Phase Clocking (TSPC) circuits in its frequency dividers is presented and through the analysis and measurement results of this synthesizer, the need for low power circuit techniques in frequency dividers is discussed. Next, Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cells are explored for implementing radio-frequency (RF) frequency dividers of low power frequency synthesizers. DCVSL ip- ops offer small input and clock capacitance which makes the power consumption of these circuits and their driving stages, very low. We perform a delay analysis of DCVSL circuits and propose a closed-form delay model that predicts the speed of DCVSL circuits with 8 percent worst case accuracy. The proposed delay model also demonstrates that DCVSL circuits suffer from a large low-to-high propagation delay ( PLH) which limits their speed and results in asymmetrical output waveforms. Our proposed enhanced DCVSL, which we call DCVSL-R, solves this delay bottleneck, reducing PLH and achieving faster operation. We implement two ring-oscillator-based voltage controlled oscillators (VCOs) in 0.13 mu m technology with DCVSL and DCVSL-R delay cells. In measurements, for the same oscillation frequency (2.4GHz) and same phase noise (-113dBc/Hz at 10MHz), DCVSL-R VCO consumes 30 percent less power than the DCVSL VCO. We also use the proposed DCVSL-R circuit to implement the 2.4GHz dual-modulus prescaler of a low power frequency synthesizer in 0.18 mu m technology. In measurements, the synthesizer exhibits -135dBc/Hz phase noise at 10MHz offset and 58 mu m settling time with 8.3mW power consumption, only 1.07mWof which is consumed by the dual modulus prescaler and the buffer that drives it. When compared to other dual modulus prescalers with similar division ratios and operating frequencies in literature, DCVSL-R dual modulus prescaler demonstrates the lowest power consumption. An all digital phase locked loop (ADPLL) that operates for a wide range of frequencies to serve as a multi-protocol compatible PLL for microprocessor and serial link applications, is presented. The proposed ADPLL is truly digital and is implemented in a standard complementary metal-oxide-semiconductor (CMOS) technology without any analog/RF or non-scalable components. It addresses the challenges that come along with continuous wide range of operation such as stability and phase frequency detection for a large frequency error range. A proposed multi-bit bidirectional smart shifter serves as the digitally controlled oscillator (DCO) control and tunes the DCO frequency by turning on/off inverter units in a large row/column matrix that constitute the ring oscillator. The smart shifter block is completely digital, consisting of standard cell logic gates, and is capable of tracking the row/column unit availability of the DCO and shifting multiple bits per single update cycle. This enables fast frequency acquisition times without necessitating dual loop fi lter or gear shifting mechanisms. The proposed ADPLL loop architecture does not employ costly, cumbersome DACs or binary to thermometer converters and minimizes loop filter and DCO control complexity. The wide range ADPLL is implemented in 90nm digital CMOS technology and has a 9-bit TDC, the output of which is processed by a 10-bit digital loop filter and a 5-bit smart shifter. In measurements, the synthesizer achieves 2.5GHz-7.3GHz operation while consuming 10mW/GHz power, with an active area of 0.23 mm2.

Considere um sistema de comunicação em que um equipamento transmissor envia pacotes de dados, de tamanho fixo e a uma taxa uniforme, a um equipamento receptor. Considere também que esses equipamentos estejam conectados por uma rede de comutação de pacotes, que introduz um atraso aleatório a cada pacote que trafega na rede. Nesta tese, é proposto um modelo de recuperação adaptativa de relógio capaz de sincronizar as frequências e as fases desses dispositivos, dentro de certos limites especificados de precisão. Esse método para atingir sincronização de frequência e de fase é baseado em medições dos tempos de chegada dos pacotes ao receptor, que são usados para controlar a dinâmica de um phase-locked loop (PLL) digital. O desempenho desse modelo é avaliado através de simulações numéricas realizadas considerando valores de parâmetros realistas. Os resultados indicam que esse esquema tem potencial para ser usado em aplicações práticas. / Consider a communication system in which a transmitter equipment sends fixed-size packets of data at a uniform rate to a receiver equipment. Consider also that these equipments are connected by a packet-switched network, which introduces a random delay to each packet. In this thesis, we propose an adaptive clock recovery scheme capable of synchronizing the frequencies and the phases of these devices, within specified limits of precision. This scheme for achieving frequency and phase synchronization is based on measurements of the packet arrival times at the receiver, which are used to control the dynamics of a digital phase-locked loop (PLL). The scheme performance is evaluated via numerical simulations performed by using realistic parameter values. The results suggest that this scheme has potential to be used in practical applications.

Nas últimas três décadas os phase locked loops (PLLs) totalmente digitais têm recebido muita atenção devido, principalmente, às vantagens que eles oferecem em comparação aos PLLs analógicos. Essas vantagens incluem melhor desempenho, maior velocidade e confiabilidade, tamanho reduzido e menor custo. Os PLLs também são amplamente utilizados em sistemas de comunicações e em outras aplicações digitais. A presente dissertação é uma contribuição no campo dos PLLs digitais adaptativos e otimizados para a sua implementação em hardware. É feito uma análise de suas características dinâmicas e proposta uma nova estrutura de PLL digital capaz de melhorar a resposta da malha em termos de tempo de aquisição e largura de banda. A Malha Síncrona Digital \"Tanlock\" com Estimação de Frequência e Ganho Adaptativo para Convergência Rápida, como é chamada, foi desenvolvida a partir da malha digital \"Tanlock\", utilizando-se teoremas de ponto fixo e mapas contrativos para determinar as condições de ganho que garantam convergência rápida e melhor utilização da largura de banda. Resultados das simulações são comparados com os obtidos teoricamente para avaliar o desempenho da malha proposta. / In the last three decades, fully-digital Phase-Locked-Loops (PLLs) systems have received a lot of attention due to its advantages in comparison with analog PLLs. These advantages include improved transient response, reliability and also reduced size and cost. The PLLs are widely used in communications systems and many other digital applications. This dissertation is a contribution to the field of digital adaptive PLLs optimized to hardware implementation. Here, a new PLL structure is presented; the Frequency Sensing Adaptive TDTL is an improvement to the classic Time-Delay Tanlock structure, alowing fast convergence to the synchronous states, using fixed-point theorems and contractive maps to determine the gain conditions which ensure the rapid convergence and also providing wider bandwidth. The results of simulations are compared with those obtained theoretically in order to assess the loop performance.