The work was based on digitally controlled oscillator for an all-digital PLL in 65nm process. Phase locked loop’s were used in most of the application for clock generation and recovery as well. As the technology grows faster in the existinggeneration, there has to be quick development with the technique. In such case ananalog PLL which was used earlier gradually getting converted to digital circuit.All-digital PLL blocks does the same work as an analog PLL blocks, but thecircuits and other control circuitry designed were completely in digital form, becausedigital circuit has many advantages over analog counterpart when they arecompared with each other. Digital circuit could be scaled down or scaled up evenafter the circuits were designed. It could be designed for low power supply voltageand easy to construct in a 65 nm process. The digital circuit was widely chosento make life easier. In most of the application PLL’s were used for clock and data recovery purpose,from that perspective jitter will stand as a huge problem for the designers. Themain aim of this thesis was to design a DCO that should bring down the jitter asdown as possible which was designed as standalone, the designed DCO would belater placed in an all-digital PLL. To understand the concept and problem aboutjitter at the early stage of the project, an analog PLL was designed in block leveland tested for different types of jitter and then design of a DCO was started. This document was about the design of a digitally controlled oscillator whichoperates with the center frequency of 2.145 GHz. In the first stage of the projectthe LC tank with NMOS structure was built and tested. In the latter stage the LCtank was optimized by using PMOS structure as negative resistance and eventuallyended up with NMOS and PMOS cross coupled structure. Tuning banks were oneof the main design in this project which plays a key role in locking the system ifthe DCO is placed in an all-digital PLL system. So, three types of tuning bankswere introduced to make the system lock more precisely. The control circuits andthe varactors built were all digital and hence it is called as digitally controlledoscillator. Digital control circuits, other sub-blocks like differential to single endedand simple buffers were also designed to optimize the signal and the results wereshown.DCO and tuning banks were tested using different types of simulation and were tested for different jitter qualities and analysis. The simulation results are shownin the final chapter simulation and results.

<p>This report is an outcome of a master degree project at Linköpings University in co-operation with Micronic Laser Systems AB. </p><p>The purpose with this master degree project was to investigate how to implement a receiver in a data transfer system. The system consists of several data channels, where every channel consists of three parts: driver, transmission lines and receiver. The driver send low amplitude differential signals via the transmission lines to the receiver that amplifies and converts it to a single-ended signal. The receiver has to be fast and be able to feed an output signal with high voltage swing. It is also needed for the receivers to have low power consumption since they are close to the load, which is sensitive to heat. </p><p>Different amplifier architectures were investigated to find a suitable circuit for the given prerequisites. In this report the advantages and disadvantages of voltage and current feedback are discussed. </p><p>The conclusions of this work are that in a system with an amplifier as a receiver with differential transmission lines, a single operational amplifier cannot be used. An input stage is needed to isolate the feedback net from the inputs of the operational amplifier. When fast rise time and large output swing are wanted the best amplifier architecture is current feedback amplifiers. A current feedback amplifier in CMOS with the required high voltages and slew rate is hard to realize without very high power consumption.</p>

This report is an outcome of a master degree project at Linköpings University in co-operation with Micronic Laser Systems AB. The purpose with this master degree project was to investigate how to implement a receiver in a data transfer system. The system consists of several data channels, where every channel consists of three parts: driver, transmission lines and receiver. The driver send low amplitude differential signals via the transmission lines to the receiver that amplifies and converts it to a single-ended signal. The receiver has to be fast and be able to feed an output signal with high voltage swing. It is also needed for the receivers to have low power consumption since they are close to the load, which is sensitive to heat. Different amplifier architectures were investigated to find a suitable circuit for the given prerequisites. In this report the advantages and disadvantages of voltage and current feedback are discussed. The conclusions of this work are that in a system with an amplifier as a receiver with differential transmission lines, a single operational amplifier cannot be used. An input stage is needed to isolate the feedback net from the inputs of the operational amplifier. When fast rise time and large output swing are wanted the best amplifier architecture is current feedback amplifiers. A current feedback amplifier in CMOS with the required high voltages and slew rate is hard to realize without very high power consumption.

Η πληθώρα των εφαρμογών που μπορεί να εξυπηρετήσει η τεχνολογία Υπερευρείας Ζώνης (UWB), από τα ασύρματα προσωπικά δίκτυα υψηλών ταχυτήτων, μέχρι τα ασύρματα δίκτυα αισθητήρων με δυνατότητες ακριβούς εντοπισμού θέσης, και τα ασύρματα δίκτυα ιατρικών αισθητήρων, έχει προκαλέσει έντονο ερευνητικό ενδιαφέρον γύρω από τις υλοποιήσεις UWB συστημάτων. Η ασυνήθιστα μεγάλη περιοχή συχνοτήτων που έχει ανατεθεί στο UWB, από τα 3.1-10.6 GHz, επιτρέπει την επίτευξη υψηλών ταχυτήτων με απλά σχήματα διαμόρφωσης, ωστόσο, λόγω της διαμοίρασης του φάσματος με τις υφιστάμενες τεχνολογίες ασύρματης δικτύωσης, οι UWB εκπομπές πρέπει να περιορίζονται σε ισχύ κάτω από το κατώφλι των -41.3 dBm/MHz, ικανοποιώντας πολύ αυστηρές μάσκες εκπομπής που εισάγουν έντονες προκλήσεις στη σχεδίαση των πομπών. Η υλοποίηση αναδιατάξιμων UWB πομπών σε σύγχρονες CMOS τεχνολογίες, με υψηλή φασματική ευελιξία, ταχύτητα και ποιότητα διαμόρφωσης, καθώς και με χαμηλή κατανάλωση, αποτέλεσε το αντικείμενο της συγκεκριμένης διατριβής. Υιοθετώντας την αρχιτεκτονική Multi-Band Impulse-Radio (MB-IR) σε συνδυασμό με την τεχνική Direct Sequence BPSK, η έρευνα προσανατολίστηκε προς την ανάπτυξη καινοτόμων μονάδων βασικής ζώνης, με στόχο την ενεργειακά αποδοτική αντιστροφή Γκαουσιανών μορφοποιημένων παλμών υψηλής ποιότητας φάσματος και διάρκειας μικρότερης ακόμα και από 1 nsec. Προς αυτή την κατεύθυνση, αναπτύχθηκε μια καινοτόμα γεννήτρια Γκαουσιανών παλμών με πολύ χαμηλούς πλευρικούς λοβούς στο φάσμα, τυπικά κάτω από -40 dB, ώστε να υποστηρίζονται οι αυστηρότερες μάσκες εκπομπής ή και μελλοντικές. Η σχεδίασης της προτεινόμενης γεννήτριας είχε ως κριτήριο την ευέλικτη ρύθμιση της διάρκειας των παραγόμενων παλμών, και αξιοποίησε τη χαρακτηριστική μεταφοράς τάσης ενός ωμικά φορτωμένου, ασύμμετρου CMOS αντιστροφέα. Η γεννήτρια βασίζεται κυρίως σε ψηφιακά κυκλώματα πολύ χαμηλής τάσης και, σε σύγκριση με τις υφιστάμενες υλοποιήσεις, παρουσιάζει σημαντικό προβάδισμα στον τομέα της ταχύτητας, καθώς και στο πλάτος εξόδου, η μεγάλη τιμή του οποίου χαλαρώνει σημαντικά τη σχεδίαση του RF front end. Η γεννήτρια μελετήθηκε διεξοδικά, διεξήχθη ανάλυση κλιμάκωσης, έγινε εξαγωγή σχεδιαστικών εξισώσεων και αναπτύχθηκαν εργαλεία λογισμικού για την αυτοματοποιημένη σχεδίασή της. Για περαιτέρω αύξηση της ταχύτητας των παλμικών σημάτων εφαρμόσθηκε ειδική σχεδίαση, η οποία αντιπραγματεύεται την ταχύτητα με το επίπεδο των λοβών του φάσματος. Για την αποδοτική BSPK διαμόρφωση των Γκαουσιανών παλμών αναπτύχθηκε ειδική τοπολογία “Μεταγωγής Σήματος Πυροδότησης Πλήρους Ισορροπίας με Up-Conversion”. Η τοπολογία αυτή, σε αντίθεση με τις ανταγωνιστικές τοπολογίες, αποφεύγει την αντιστροφή του παλμού με αναλογικά κυκλώματα υψηλής κατανάλωσης, αλλά και την αναλογική μεταγωγή, καθώς η διαμόρφωση λαμβάνει χώρα πριν από την παραγωγή των παλμών. Παράλληλα, επιτυγχάνονται υψηλοί ρυθμοί, καθώς και υψηλή ποιότητα διαμόρφωσης λόγω των ισορροπημένων μονοπατιών της τοπολογίας. Η γεννήτρια μαζί με το διαμορφωτή αποτελούν τις καινοτόμες παρεμβάσεις στη μονάδα Βασικής Ζώνης του προτεινόμενου πομπού. Για την ολοκλήρωση της λειτουργικότητας του πομπού, αναπτύχθηκε ένα RF front end, το οποίο αποτελείται από έναν διπλά ισορροπημένο μίκτη, έναν LO buffer, ένα μετατροπέα διαφορικού σήματος σε απλό, και έναν ενισχυτή ισχύος, ο οποίος είναι προσαρμοσμένος στα 50 Ohms, χωρίς να απαιτεί κανένα εξωτερικό στοιχείο. Το RF front end ολοκληρώθηκε μαζί με τη μονάδα βασικής ζώνης, και ο ολοκληρωμένος πομπός κατασκευάστηκε σε τεχνολογία CMOS 130 nm. Το ολοκληρωμένο προσαρτήθηκε στην RF πλακέτα συστήματος με την τεχνική Chip on Board. Για την επιτυχία του συστήματος με την πρώτη προσπάθεια έγινε συσχεδίαση σε επίπεδο IC-Package-PCB, δίνοντας ιδιαίτερη έμφαση στα ζητήματα Signal/Power Integrity. Ο πομπός παρουσίασε την υψηλότερη ταχύτητα από τις ανταγωνιστικές MB-IR UWB υλοποιήσεις, ίση με 1.5 Gbps, με αντίστοιχη ενεργειακή αποδοτικότητα 21 pJoule/bit και μέτρο διανυσματικού σφάλματος 5.5%. Ο πομπός βελτίωσε τους πλευρικούς λοβούς στο φάσμα περισσότερο από 10 dB, ενώ η διατριβή, εκμεταλλευόμενη την αναδιαταξιμότητα του πομπού, παρουσιάζει, επιπλέον, τις πρώτες μετρήσεις σε ταχύτητες εκατοντάδων Mbps για ικανοποίηση της χαμηλής ζώνης της πρόσφατα θεσμοθετημένης, και εξαιρετικά αυστηρής, ευρωπαϊκής μάσκας εκπομπής. / The multitude of applications that Ultra-Wideband (UWB) technology can serve, from high-speed Wireless Personal Area Networks, to Wireless Sensor Networks with precision Geolocation abilities, and Wireless Medical Networks, has attracted intense research interest in the implementation of UWB systems. The unusually wide range of frequencies assigned to UWB, from 3.1-10.6 GHz, allows UWB systems employing low order modulation schemes to enjoy high throughput at low power consumption. However, since UWB shares the spectrum with existing wireless networking technologies, UWB emissions must be limited to a power spectral density below the threshold of -41.3 dBm/MHz, satisfying very stringent emission masks and introducing great challenges in the design of UWB transmitters. The subject of this thesis is the design of low power, fully integrated, reconfigurable CMOS UWB transmitters, with high spectral flexibility, high speed and high modulation quality. Adopting the Multi-Band Impulse-Radio architecture, in conjunction with the Direct Sequence BPSK modulation, the research focused on the development of a baseband unit, able to precisely invert Gaussian shaped, subnanosecond pulses. The key contributions of this thesis are a CMOS Gaussian Pulse Generator and a BSPK modulation topology, which jointly constitute the proposed baseband unit. The Pulse Generator (PG) is based on non-linear shaping, so as to facilitate the configurability of the output pulse duration, and exploits the voltage transfer characteristic of a Resistive Loaded Asymmetrical CMOS Inverter, which results in spectral sidelobes typically better than -40 dB. The PG incorporates mostly-digital low voltage circuits, while the MOSFET devices that undertake the pulse shaping avoid exclusive operation in weak inversion, in contrast to previous implementations. Consequently, the proposed CMOS PG is able to support higher throughput, as well as higher output amplitude, which relaxes considerably the design of the RF front end. This thesis presents a systematic design procedure and a scaling analysis of the non-linear pulse shaper. Moreover, in order to further increase the speed, a special PRF boost technique is proposed, which trades off speed and spectral efficiency for the spectral sidelobes level. Regarding the BPSK modulator, this work introduces the “Trigger Switching Fully Balanced Up-Conversion” topology, which avoids the use of power-hungry and distortion-prone analog circuits for the accurate inversion of the subnanosecond shaped pulses, as well as avoids the application of analog waveform switching to the baseband pulses, since the baseband modulation takes place before the generation of the pulses. The digital nature of the switching lends itself to high data rates, while the balanced paths of the topology ensure high modulation quality with minimal design effort. Wafer probing measurements confirmed the high performance of the baseband unit. The functionality of the transmitter was completed by the development of an RF front end which consists of a double balanced mixer, an LO buffer, a differential to single-ended (DtoSE) converter, and a power amplifier which is ready to drive a 50 Ohms load without requiring any off-chip components. The integrated transmitter, which incorporates the proposed baseband unit and the RF front end, was fabricated in 130 nm CMOS technology. The transmitter RFIC was directly attached to the system RF PCB using the Chip-on-Board packaging option. The First-Pass success of the system was ensured by paying particular attention to Signal/Power Integrity issues and following an IC-Package-PCB co-design procedure. The transmitter was measured up to 1.5 Gbps, which, to the author’s knowledge, was the highest speed amongst the competitive Multi-Band Impulse-Radio UWB implementations in the literature. The corresponding energy efficiency was 21 pJoule/bit and the Error Vector Magnitude (EVM) 5.5%, while the proposed transmitter improved the spectral sidelobes by over 10 dB. Exploiting the reconfigurability of the transmitter, this thesis presents the first measurements at multi-Mbps speeds that completely meet the final version of the European spectrum emission mask.