Low power, high speed serial transceivers are employed in a wide range of applications ranging from chip-to-chip, backplane, and optical interconnects. Apart from being capable of handling a wide range of data rates, the transceivers should have low power consumption (mW/Gbps) and be fully integrated. This work discusses enabling techniques to implement such transceivers. Specifically, three designs: (1) a 0.5-4 Gbps serial link which uses current recycling to reduce power dissipation and (2) a 0.5-2.5 Gbps reference-less clock and data recovery circuit which uses a novel frequency detector to achieve unlimited acquisition range and (3) a 2-4 Gbps low power receiver architecture capable of resolving multiple signalling formats with a simplified XOR based phase rotating PLL will be presented. All the three circuit topologies are highly digital and aim to address the requirements of wide operating range, low power dissipation while being fully integrated. Measured results obtained from the prototypes illustrate the effectiveness of the proposed design techniques. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from Dec. 2, 2011 - June 2, 2012

Nas últimas três décadas os phase locked loops (PLLs) totalmente digitais têm recebido muita atenção devido, principalmente, às vantagens que eles oferecem em comparação aos PLLs analógicos. Essas vantagens incluem melhor desempenho, maior velocidade e confiabilidade, tamanho reduzido e menor custo. Os PLLs também são amplamente utilizados em sistemas de comunicações e em outras aplicações digitais. A presente dissertação é uma contribuição no campo dos PLLs digitais adaptativos e otimizados para a sua implementação em hardware. É feito uma análise de suas características dinâmicas e proposta uma nova estrutura de PLL digital capaz de melhorar a resposta da malha em termos de tempo de aquisição e largura de banda. A Malha Síncrona Digital \"Tanlock\" com Estimação de Frequência e Ganho Adaptativo para Convergência Rápida, como é chamada, foi desenvolvida a partir da malha digital \"Tanlock\", utilizando-se teoremas de ponto fixo e mapas contrativos para determinar as condições de ganho que garantam convergência rápida e melhor utilização da largura de banda. Resultados das simulações são comparados com os obtidos teoricamente para avaliar o desempenho da malha proposta. / In the last three decades, fully-digital Phase-Locked-Loops (PLLs) systems have received a lot of attention due to its advantages in comparison with analog PLLs. These advantages include improved transient response, reliability and also reduced size and cost. The PLLs are widely used in communications systems and many other digital applications. This dissertation is a contribution to the field of digital adaptive PLLs optimized to hardware implementation. Here, a new PLL structure is presented; the Frequency Sensing Adaptive TDTL is an improvement to the classic Time-Delay Tanlock structure, alowing fast convergence to the synchronous states, using fixed-point theorems and contractive maps to determine the gain conditions which ensure the rapid convergence and also providing wider bandwidth. The results of simulations are compared with those obtained theoretically in order to assess the loop performance.

Considere um sistema de comunicação em que um equipamento transmissor envia pacotes de dados, de tamanho fixo e a uma taxa uniforme, a um equipamento receptor. Considere também que esses equipamentos estejam conectados por uma rede de comutação de pacotes, que introduz um atraso aleatório a cada pacote que trafega na rede. Nesta tese, é proposto um modelo de recuperação adaptativa de relógio capaz de sincronizar as frequências e as fases desses dispositivos, dentro de certos limites especificados de precisão. Esse método para atingir sincronização de frequência e de fase é baseado em medições dos tempos de chegada dos pacotes ao receptor, que são usados para controlar a dinâmica de um phase-locked loop (PLL) digital. O desempenho desse modelo é avaliado através de simulações numéricas realizadas considerando valores de parâmetros realistas. Os resultados indicam que esse esquema tem potencial para ser usado em aplicações práticas. / Consider a communication system in which a transmitter equipment sends fixed-size packets of data at a uniform rate to a receiver equipment. Consider also that these equipments are connected by a packet-switched network, which introduces a random delay to each packet. In this thesis, we propose an adaptive clock recovery scheme capable of synchronizing the frequencies and the phases of these devices, within specified limits of precision. This scheme for achieving frequency and phase synchronization is based on measurements of the packet arrival times at the receiver, which are used to control the dynamics of a digital phase-locked loop (PLL). The scheme performance is evaluated via numerical simulations performed by using realistic parameter values. The results suggest that this scheme has potential to be used in practical applications.

This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442μW with 1.2V power supply. Measured integral nonlinearity and differential nonlinearity are 0.5LSB and 0.33LSB respectively.

No description available.

Following the rise of Internet of Things (IoT), or just the technological advancements and expectations in a world where the things are or will be connected, new demands are put on Integrated Circuit (IC) for wireless connectivity. The use cases seem endless; smart home, healthcare, entertainment, and science are all areas that can benefit from connectivity of low power electronics. But there are obstacles to overcome. Meeting the specifications, especially the phase noise requirements of modern high-speed wireless standards can be a challenge for devices that run on low supply voltages and are allowed only very limited power consumption. The focus of this thesis is the exploration of modern LC-oscillator architectures for RF-transceivers, and the design and post-layout evaluation of a Digitally Controlled Oscillator (DCO) intended to be used in an All-Digital Phase Locked Loop (ADPLL) in a 22 nm FD-SOI process. The DCO specifications are set by an ADPLL for the Wi-Fi 6 (MCS 11) standard. The ADPLL is replacing the blocks that are usually implemented as noise-sensitive analog components with more robust digital blocks that are easier to integrate with baseband- and digital-circuitry. A dual-core class-C oscillator with a dynamic-biasing circuit is proposed and designed to meet the specification of -121 dBc/Hz phase noise at a 1 MHz offset from 7.8 GHz, a –7.18.6 GHz tuning range, and a frequency resolution of at most 35 kHz around 7.8 GHz. The phase noise specification is met; a phase noise of -121 dBc/Hz at the 1 MHz offset from 7.8 GHz is achieved in post-layout simulation along with a Figure of Merit (FoM) of 189.9, and an average tracking frequency step of 5.8 MHz. The tuning range specification was not met, but it is reasonable to believe that the specified range can be met after some redesign of the capacitor banks. Further work will be required. / Till följd av tillväxten inom Internet of Things (IoT), eller bara de teknologiska framgångar och förväntningar på en värld där dem flesta saker är eller kommer att bli uppkopplade, ställs nya krav på Integrated Circuit (IC)-komponenter för trådlös uppkoppling. Tillämningsområdena är oändliga; smart home, sjukvård och hälsa, underhållning och forskning är områden som som kan dra nytta av nya uppkopplingsmöjligheter med extremt strömsnål elektronik. Att leva upp till specifikationerna för moderna trådlösa höghastighetsuppkopplingar, speciellt när det kommer till fasbrus, kan dock vara en utmaning för enheter som måste klara sig med en väldigt begränsad effektåtgång. Fokus för denna avhandling är design och utvärdering på schematik och layout-nivå av en Digitally Controlled Oscillator (DCO) för en 22 nm Fully Depleted Silicon-On-Insulator (FD-SOI)-process avsedd att klara specifikationen satt av en given All-Digital Phase Locked Loop (ADPLL) för Wi-Fi 6 (MCS 11) standarden. En DCO och ADPLL ersätter block som tidigare tillämpats som analoga bruskänsliga komponenter med robustare digitala komponenter som är enklare att integrera med bas-band och digital logik-kretsar. En dubbelkärnig klass-C DCO med en dynamisk biaskrets föreslås för att nå kravet på fasbrus på maximalt -121 dBc/Hz mätt vid 1 MHz från en frekvens på 7.8 GHz, med ett frekvensomfång 7.1-8.6 GHz och en frekvensupplösning under 35 kHz. Fasbruset vid denna 1 MHz från 7.8 GHz uppmättes i simulering till -121 dBc/Hz, och en Figure of Merit (FoM) på 189.9 har uppnåtts, samt en genomsnittlig frekvensupplösning på 5.8 MHz nära 7.8 GHz. Designen klarar inte av att möta kraven på frekvensomfång, men det är sannolikt att en liknande design kan möta specifikationen efter ytterligare revision. Ytterligare arbete krävs.

Desire for low-power, high performance computing has been at core of the symbiotic union between digital circuits and CMOS scaling. While digital circuit performance improves with device scaling, analog circuits have not gained these benefits. As a result, it has become necessary to leverage increased digital circuit performance to mitigate analog circuit deficiencies in nanometer scale CMOS in order to realize world class analog solutions. In this thesis, both circuit and system enhancement techniques to improve performance of clock generators are discussed. The following techniques were developed: (1) A digital PLL that employs an adaptive and highly efficient way to cancel the effect of supply noise, (2) a supply regulated DPLL that uses low power regulator and improves supply noise rejection, (3) a digital multiplying DLL that obviates the need for high-resolution TDC while achieving sub-picosecond jitter and excellent supply noise immunity, and (4) a high resolution TDC based on a switched ring oscillator, are presented. Measured results obtained from the prototype chips are presented to illustrate the proposed design techniques. / Graduation date: 2013 / Access restricted to the OSU Community at author's request from July 16, 2012 - July 16, 2014