Abstract The aim of this work was to improve the performance and usability of a digital time-to-digital converter (TDC) in CMOS technology. The characteristics of the TDC were improved especially for the needs of pulsed laser time-of-flight (TOF) distance measurement, where picosecond-level precision with a long µs-level measurement range is needed in order to approach mm-level measurement accuracy. Stability in the face of process, voltage and temperature variations, multiple measurement channels, alternative measurement modes, a high integration level, standard interfaces and simple usage were the main features for development. The measurement architecture is based on counter and timing signal interpolation on two levels. The counter counts the full reference clock cycles between the timing signals, while a new recycling delay line developed in this thesis interpolates within the reference clock cycle. This technique utilizes a short delay line several times per reference clock cycle, which minimizes the interpolation nonlinearity. The same structure also makes the use of a low, MHz-level reference frequency possible, and thus only a crystal is needed as an external oscillator component. The parallel load capacitor-scaled delay line structure acts as the second, sub-gate-delay interpolation level. The INL does not accumulate in elements connected in parallel, and the load capacitance differences enable high, ps-level resolution to be achieved. Four TDC circuits in 0.35 µm CMOS technology were designed and tested in the course of this work, of which the latest, a 7-channel TDC, is able to measure the time intervals between the start pulse and three separate stop pulses in one measurement and to resolve the pulse widths or rise times at the same time. In laser TOF distance measurement this functionality can be used when several echoes arrive at the receiver, and also to compensate for the detection threshold problem known as timing walk error. The TDC achieves 8.9 ps interpolation resolution within the cycle time of a 20 MHz reference clock using only 8 delay elements on the first interpolation level and 14 delay elements on the second. A measurement precision better than 9 ps was achieved without using result post-processing or look-up tables. This work shows that versatile, high performance TDCs can be created in standard CMOS technology. / Tiivistelmä Väitöskirjatyön tavoitteena oli parantaa CMOS-aika-digitaalimuuntimien suorituskykyä ja käytettävyyttä. Muuntimen ominaisuuksia kehitettiin erityisesti laseretäisyysmittauksen tarpeita ajatellen, missä millimetritason mittaustarkkuus laajalla mittausaluella edellyttää aika-digitaalimuuntimelta pikosekuntitason tarkkuutta mikrosekuntien mittausalueella. Stabiilius prosessiparametri-, jännite- ja lämpötilavaihteluita vastaan, useat mittauskanavat, useat mittausmoodit, korkea integraatioaste, standardoidut liitäntäväylät ja helppo käytettävyys olivat erityisesti kehityksen kohteina. Suunniteltu mittausarkkitehtuuri koostuu laskurista ja kaksitasoisesta ajoitussignaali-interpolaattorista. Laskuri laskee kokonaiset referenssikellojaksot ajoitussignaalien välillä ja työssä kehitetty referenssiä kierrättävä viivelinjarakenne rekistereineen interpoloi ajoitussignaalien paikat referenssikellojaksojen sisältä. Referenssinkierrätystekniikka hyödyntää lyhyttä viivelinjaa useampaan kertaan kellojakson aikana, mikä minimoi epälineaarisuuden interpoloinnissa. Sama rakenne mahdollistaa myös MHz-tason referenssitaajuuden, jolloin matalataajuista kidettä voidaan käyttää referenssilähteenä. Toinen interpolointitaso koostuu rinnakkaisista kapasitanssiskaalatuista viive-elementeistä, mitkä mahdollistavat alle porttiviiveen mittausresoluution. Rinnakkaisessa rakenteessa elementtien epälineaarisuudet eivät summaudu, mikä mahdollistaa pikosekuntitason mittaustarkkuuden. Väitöskirjatyössä suunniteltiin ja toteutettiin neljä aikavälinmittauspiiriä käyttäen 0,35 µm CMOS-teknologiaa, joista viimeisin, 7-kanavainen muunnin kykenee mittaamaan aikavälin useampaan pulssiin yhdellä kertaa sekä voi selvittää samalla pulssien leveydet tai nousuajat. Laseretäisyysmittauksessa monikanavaisuutta voidaan käyttää kun useita kaikuja lähetetystä pulssista saapuu vastaanottimeen sekä kompensoimaan mittauksessa esiintyviä muita virhelähteitä. Käytettäessä 20 MHz:n kidettä referenssilähteenä muunnin saavuttaa alle 9 ps:n interpolointiresoluution ja tarkkuuden ilman epälineaarisuudenkorjaustaulukoita. Työ osoittaa, että edullisella CMOS-teknologialla voidaan toteuttaa monipuolinen ja erittäin suorituskykyinen aika-digitaalimuunnin.

This thesis proposes and demonstrates Time to Digital Converters (TDC) with high resolution realized in 65-nm digital CMOS. It is used as a phase detector in all digital PLL working with 5GHz DCO and 20MHz reference input for radio transmitters. Two kinds of high resolution TDC are designed on schematic level including Vernier TDC and parallel TDC. The Sensed Amplifier Flip Flop (SAFF) is implemented with less than 1ps sampling window to avoid metastability. The current starved delay elements are adopted in the TDC and the conversion resolution is equal to the difference of the delay time from these delay elements. Furthermore, the parallel TDC is realized on layout and finally achieves the resolution of 3ps meanwhile it consumes average power 442μW with 1.2V power supply. Measured integral nonlinearity and differential nonlinearity are 0.5LSB and 0.33LSB respectively.

Vision has always been one of the most important cognitive tools of human beings. In this regard, the development of image sensors opens up the potential to view objects that our eyes cannot see. One of the most promising capability in some image sensors is their single-photon sensitivity that provides information at the ultimate fundamental limit of light. Time-resolved single-photon avalanche diode (SPAD) image sensors bring a new dimension as they measure the arrival time of incident photons with a precision in the order of hundred picoseconds. In addition to this characteristic, they can be fabricated in complementary metal-oxide-semiconductor (CMOS) technology enabling the integration of complex signal processing blocks at the pixel level. These unique features made CMOS SPAD sensors a prime candidate for a broad spectrum of applications. This thesis is dedicated to the optimization and characterization of quantum imagers based on the SPADs as part of the E.U. funded SUPERTWIN project to surpass the fundamental diffraction limit known as the Rayleigh limit by exploiting the spatio-temporal correlation of entangled photons. The first characterized sensor is a 32×32-pixel SPAD array, named “SuperEllen”, with in-pixel time-to-digital converters (TDC) that measure the spatial cross-correlation functions of a flux of entangled photons. Each pixel features 19.48% fill-factor (FF) in 44.64-μm pitch fabricated in a 150-nm CMOS standard technology. The sensor is fully characterized in several electro-optical experiments, in order to be used in quantum imaging measurements. Moreover, the chip is calibrated in terms of coincidence detection achieving the minimal coincidence window determined by the SPAD jitter. The second developed sensor in the context of SUPERTWIN project is a 224×272-pixel SPAD-based array called “SuperAlice”, a multi-functional image sensor fabricated in a 110-nm CMOS image sensor technology. SuperAlice can operate in multiple modes (time-resolving or photon counting or binary imaging mode). Thanks to the digital intrinsic nature of SPAD imagers, they have an inherent capability to achieve a high frame rate. However, running at high frame rate means high I/O power consumption and thus inefficient handling of the generated data, as SPAD arrays are employed for low light applications in which data are very sparse over time and space. Here, we present three zero-suppression mechanisms to increase the frame rate without adversely affecting power consumption. A row-skipping mechanism that is implemented in both SuperEllen and SuperAlice detects the absence of SPAD activity in a row to increase the duty cycle. A current-based mechanism implemented in SuperEllen ignores reading out a full frame when the number of triggered pixels is less than a user-defined value. A different zero-suppression technique is developed in the SuperAlice chip that is based on jumping through the non-zero pixels within one row. The acquisition of TDC-based SPAD imagers can be speeded up further by storing and processing events inside the chip without the need to read out all data. An on-chip histogramming architecture based on analog counters is developed in a 150-nm CMOS standard technology. The test structure is a 16-bin histogram with 9 bit depth for each bin. SPAD technology demonstrates its capability in other applications such as automotive that demands high dynamic range (HDR) imaging. We proposed two methods based on processing photon arrival times to create HDR images. The proposed methods are validated experimentally with SuperEllen obtaining >130 dB dynamic range within 30 ms of integration time and can be further extended by using a timestamping mechanism with a higher resolution.