Integrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions. / text

The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. The advantage of using a fully digital ADC design rather than a traditional analog ADC design is that the circuit is defined by an HDL description and automatically synthesized by tools. It offers low power consumption, low silicon area and a fully optimized gate-level circuit that reduces the design costs, etc. The functioning of an all-digital ADC is based on the time domain signal processing approach, which brings a high time resolution obtained by the use of a nanometer CMOS process. An all-digital ADC design is implemented by using a combination of the digital Voltage-Controlled Oscillator (VCO) and a Time-to-Digital Converter (TDC). The VCO converts the amplitude-domain analog signal to a phase-domain time-based signal. In addition, the VCO works as a time based quantizer. The time-based signal from the VCO output is then processed by the TDC quantizer in order to generate the digital code sequences. The fully digital VCO-based ADC has the advantage of superior time resolution. Moreover, the VCO-based ADC offers a first order noise shaping property of its quantization noise. This thesis presents the implementation of a VCO-based ADC in STM 65 nm CMOS process technology using digital tools such as ModelSim simulator, Synopsys Design Compiler and Cadence SOC Encounter. The circuit level simulations have been done in Cadence Virtuoso ADE. A multi-phase VCO and multi-bit quantization architecture has been chosen for this 8-bit ADC. The power consumption of the ADC is approximately 630 μW at 1.0 V power supply and the figure of merit is around 410 fJ per conversion step.

In today's world, most automobiles use Controller Area Network (CAN) bus for communication between various Electronic Control Units (ECUs), also called nodes on the CAN bus. Each ECU on the CAN bus is a microcontroller that sends a unique identifier used for node identification. It is possible to spoof node A by sending the same identifier through node B and thereby control node A. Thus, a hacker can control the steering using the car's internal lights and render it ineffective or misuse them. In order to combat this, we try to fingerprint each node by identifying its identifier's unique bit timing characteristics. To that extent, bit timing characteristics used are the Time of Flight (TOF) intervals between successive rising edges of identifier bits, for an ECU. Similarly, other characteristics such as TOF between successive falling edges of the CAN bus node identifier can also be used for node classification. In order to measure these TOFs, we use a device called Time-to-Digital Convertor, which essentially triggers a ring oscillator to measure time values between rising/falling edges of a signal, to the order of picosecond accuracy. These timing values are used as features into the K-nearest neighbors (KNN) classifier algorithm. Once the classifier is trained, it can be used to predict a new timing value into a particular node category, which if different from the expected category is a sign of compromise or intrusion. It is seen that we achieve 95% accuracy of correctly predicting the compromised node under simulation tests. Thereafter, the thesis deals with experimentally predicting an intrusion in the CAN bus system utilizing EPOS Studio CAN bus position controller for Maxon motors. The clock timings being extremely accurate leads to the conclusion that employment of better statistical techniques for node characterization is needed for intrusion detection, which is outside the scope of this work. / Master of Science / In today’s world, most automobiles use Controller Area Network (CAN) bus for communication between various Electronic Control Units (ECUs), also called nodes on the CAN bus. These nodes can range from car headlights, radio, doors, internal lights to brakes, steering, throttle and much more. Each node on the CAN bus is a microcontroller which controls its proper operation. This also means that if a node is compromised using external hardware or a piece of software, it could be quite risky. Thus, a hacker can control the steering using the car’s internal lights and render it ineffective or misuse them. In order to combat this, we try to fingerprint each node by identifying its unique time domain characteristics. These characteristics can be the Time of Flight (TOF) measurement values between successive rising or falling edges of a node’s unique identifier, using an instrument called a Time-to-Digital convertor. Furthermore, these TOF values are used as features for the K-nearest neighbor (KNN) classifier machine learning algorithm, which uniquely identifies signals coming from any of the fingerprinted nodes, thereby raising a flag if a message comes from an unidentified node. In addition, experimental data is obtained for node identifiers on the CAN bus, in digital form, and passed into a neural network (NN) for training the classifier. We achieve an 95% and 70% prediction accuracy for the KNN and NN classifiers respectively.

A major pathway of tyramine and dopamine synthesis in insects is through the decarboxylation of tyrosine and DOPA, respectively. Although tyrosine decarboxylase (TDC) has been mentioned in some reports, it has never been critically analyzed. The high sequence identity shared by tyrosine decarboxylase and DOPA decarboxylase in insects, and the similar structures of the substrates, tyrosine and DOPA, raise the possibility that both tyrosine decarboxylase and DOPA decarboxylase (DDC) have activities to tyrosine and DOPA. In this study, after tyrosine decarboxylase and DOPA decarboxylase enzymes of Anopheles gambiae were expressed, their substrate specificities and biochemical properties were critically analyzed. My results provide clear biochemical evidence establishing that the mosquito tyrosine decarboxylase functions primarily on the production of tyramine with low activity to DOPA. In contrast, mosquito DOPA decarboxylase is highly specific to DOPA with essentially no activity to tyrosine. / Master of Science in Life Sciences

Nous présentons une caméra à balayage de fente intégrée basée sur un système de comptage de photon unique résolu en temps (TCSPC-SC) employant l'architecture linéaire « streak » pour surmonter la limitation de l'espace inhérent aux systèmes TCSPC bidimensionnels. Cette solution permet l'intégration de fonctionnalités électroniques complexes dans les pixels sans l'inconvénient d'un faible facteur de remplissage conduisant à une faible efficacité de détection. Le TCSPC-SC se compose de deux blocs principaux: une photodiode à avalanche (SPAD) et un bloc de mesure de temps, les deux blocs sont intégrés en technologie 180 nm CMOS standard. La structure de la SPAD utilisée a été sélectionnée parmi 6 structures différentes après un processus de caractérisation précise et approfondie. Le bloc de mesure du temps se compose d'un TOC hybride capable d'atteindre des résolutions de temps élevées et ajustables avec une large dynamique de mesure grâce à un système de conversion de temps (TOC) hybride qui combine l'approche analogique basée sur un convertisseur de temps vers amplitude(TAC), et les approches numériques utilisant une boucle à verrouillage de retard (DLL) et un compteur numérique. Le TOC hybride a été spécialement conçu pour être utilisé dans un système TCSPC qui intègre une ligne de TOC nécessitant ainsi une conception appropriée pour limiter la consommation d'énergie et la surface d'occupation et parvenir à une architecture flexible et facilement extensible. Suite à la conception et la réalisation de ces deux blocs dans une technologie180 nm CMOS standard, une structure de test de la caméra à balayage de fente (TCSPC-SC) qui englobe 8 unités a été réalisée dans le but final de mettre en œuvre un modèle TCSPC-SC complet et plus large. / In this work we present a TCSPC Streak Camera (TCSPC-SC) that takes advantage of the streak mode imaging ta overcome the space limitation inherent ta 20 TCSPC sensor arrays. This cost-effective solution allows the integration of complex functionalities in the pixel without the inconvenience of low fill factor that leads ta low detection efficiency. The TCSPC~SC consists of two main building blacks: a SPAD and a time measurement black bath integrated in 180 nm Standard CMOS technology. The SPAD was selected among 6 different SPAD structures following a thorough characterization process ta fully determine its performance figures. The time measurement black consists of a hybrid TOC capable of achieving high adjustable time resolutions with large dynamic range owing ta a time conversion scheme that combines traditional Analog Time to Amplitude Converter (TAC), Digital DLL-based and counter-based TOC. Furthermore, thehybrid TOC was especially designed ta be used in a TCSPC system that incorporates an array of TDCs which required a careful design ta limit power consumption and occupation area in order to achieve a flexible and easily scalable architecture. These two building blacks were bath fabricated in a 180 nm standard CMOS technology and employed ta demonstrate a TCSPC Streak Camera(TCSPC-SC) test structure that englobes 8 units in order ta demonstrate the system's operation principle with the final aim of implementing a complete and bigger TCSPC-SC model in the near future

La mesure de temps de vol de photons et/ou de temps de propagation d’ondes RF et ultra large bande est devenue une technique essentielle et indispensable pour de nombreuses applications telles qu’en géolocalisation en intérieur, en détection LASER et en imagerie biomédicale, notamment en tomographie optique diffuse (TOD) avec des mesures dans le domaine temporel (DT). De telles mesures nécessitent des convertisseurs temps-numérique aptes à mesurer des intervalles de temps très courts avec grande précision, et ce, à des résolutions temporelles allant de quelques picosecondes à quelques dizaines de picosecondes. Les scanners TOD-DT ont généralement recours à des cartes électroniques de comptage de photons uniques intégrant essentiellement des convertisseurs temps-numérique hybrides (un mixte de circuits monolithiques et non-monolithiques). Dans le but de réduire le temps d’acquisition de ces appareils et d’augmenter leur précision, plusieurs mesures à différentes positions et longueurs d’ondes doivent pouvoir être effectuées en parallèle, ce qui exige plusieurs cartes de comptage de photons. L’implémentation de tels dispositifs en technologie CMOS apporte de multiples avantages particulièrement en termes de coût, d’intégration et de consommation de puissance. Cette thèse apporte une solution architecturale d’un convertisseur temps-numérique à 10-bits dédié aux applications de TOD-DT. Le convertisseur réalisé en technologie CMOS 0,13 μm d’IBM et occupant une surface en silicium de 1,83 x 2,23 mm[indice supérieur 2] incluant les plots de connexion, présente une résolution temporelle de 12 ps sur une fenêtre de 12 ns pour une consommation en courant de 4,8 mA. Les avantages de l’architecture proposée par rapport à d’autres réalisations rapportées dans la littérature résident dans son immunité face aux variations globales du procédé de fabrication, l’indépendance de la résolution temporelle vis-à-vis de la technologie ciblée et la faible gigue temporelle qu’il présente. Le circuit intégré réalisé trouvera plusieurs champs d’applications autres que la TOD notamment dans les tomographes d’émission par positrons, les boucles à verrouillage de phase numériques et dans les systèmes de télédétection et d’imagerie 3D.

Time-to-digital converters (TDC) are widely used in light-detection-and-ranging (LIDAR) systems to measure the time-of-flight. Conventional TDCs are sensitivity to process, voltage, and temperature (PVT) variations. Recent work utilizing the stochastic delay-line TDC architecture has demonstrated excellent robustness against PVT variations. But important issues affecting the linearity of a stochastic delay-line TDC has yet to be recognized and addressed.This thesis rigorously analyzes the problem of linearity of a stochastic delay-line TDC and formulates an intuitive theory to predict the linearity performance. Apolarvisualization of the phase distribution of a delay line is proposed to aid the analysis. Based on the results of this study, this thesis proposes a stochastic delay-line TDC employing a delay-locked loop (DLL) to guarantee linearity over PVT variations and to reduce the number of redundant bits. The proposed TDC is implemented in a 0.18 µm CMOS process to validate the linearity theory and the proposed solution. The 8-bit TDC samples at 60 MHz and demonstrates a linear-number-of-bit of 6.36 with only 2-bit redundancy. Consuming 25 mW from a 1.8 V supply, the TDC yields a figure-of-merit of 5.04 pJ/conversion-step. With the DLL turned off, the integral nonlinearity (INL) degrades by about a factor of two, verifying the effectiveness of the proposed solution. The TDC is measured at different temperatures and supply voltages to demonstrate robustness against PVT variations. The measurement results show excellent agreement with the behavioral simulations.

No description available.

No description available.

Abstract This thesis describes the development of a high precision time-to-digital converter (TDC) in which the conversion is based on a counter and three-stage stabilised delay line interpolation developed in this work. The biggest design challenges in the design of a TDC are related to the fact that the arrival moment of the hit signals (start and stop) is unknown and asynchronous with respect to the reference clock edges. Yet, the time interval measurement system must provide an immediate and unambiguous measurement result over the full dynamic range. It must be made sure that the readings from the counter and the interpolators are always consistent with very high probability. Therefore, the operation of the counter is controlled with a synchronising logic that is in turn controlled with the interpolation result. Another synchronising logic makes it possible to synchronise the timing signals with multiphase time-interleaved clock signals as if the synchronising was done with a GHz-level clock, and enables multi-stage interpolation. Multi-stage interpolation reduces the number of delay cells and registers needed. The delay line interpolators are stabilised with nested delay-locked loops, which leads to good stability and makes it possible to improve single-shot precision with a single look-up table containing the integral nonlinearities of the interpolators measured at the room temperature. A multi-channel prototype TDC was fabricated in a 0.6 μm digital CMOS process. The prototype reaches state-of-the-art rms single-shot precision of better than 20 ps and low power consumption of 50 mW as an integrated TDC.