The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. The advantage of using a fully digital ADC design rather than a traditional analog ADC design is that the circuit is defined by an HDL description and automatically synthesized by tools. It offers low power consumption, low silicon area and a fully optimized gate-level circuit that reduces the design costs, etc. The functioning of an all-digital ADC is based on the time domain signal processing approach, which brings a high time resolution obtained by the use of a nanometer CMOS process. An all-digital ADC design is implemented by using a combination of the digital Voltage-Controlled Oscillator (VCO) and a Time-to-Digital Converter (TDC). The VCO converts the amplitude-domain analog signal to a phase-domain time-based signal. In addition, the VCO works as a time based quantizer. The time-based signal from the VCO output is then processed by the TDC quantizer in order to generate the digital code sequences. The fully digital VCO-based ADC has the advantage of superior time resolution. Moreover, the VCO-based ADC offers a first order noise shaping property of its quantization noise. This thesis presents the implementation of a VCO-based ADC in STM 65 nm CMOS process technology using digital tools such as ModelSim simulator, Synopsys Design Compiler and Cadence SOC Encounter. The circuit level simulations have been done in Cadence Virtuoso ADE. A multi-phase VCO and multi-bit quantization architecture has been chosen for this 8-bit ADC. The power consumption of the ADC is approximately 630 μW at 1.0 V power supply and the figure of merit is around 410 fJ per conversion step.

This thesis explores the study and design of an all-digital VCO-based ADC in a 65 nm CMOS technology. As the CMOS process enters the deep submicron region, the voltage-domain-based ADCs begins to suffer in improving their performance due to the use of complex analog components. A promising solution to improve the performance of an ADC is to employ as many as possible digital components in a time-domain-based ADC, where it uses the time resolution of an analog signal rather than the voltage resolution. In comparison, as the CMOS process scales down, the time resolution of an analog signal has found superior than the voltage resolution of an analog signal. In recent years, such time-domain-based ADCs have been taken an immense interest due to its inherent features and their design reasons. In this thesis work, the VCO-based ADC design, falls under the category of time-based ADCs which consists of a VCO and an appropriate digital processing circuitry. The employed VCO is used to convert a voltage-based signal into a time signal and thereby it also acts as a time-based quantizer. Then the resulting quantized-time signal is converted into a digital signal by an appropriate digital technique. After different architecture exploration, a conventional VCO-based ADC architecture is implemented in a high-level model to understand the characteristic behaviour of this time-based ADC and then a comprehensive functional schematic-level is designed in reference with the implemented behavioural model using cadence design environment. The performance has been verified using the mixed-levels, of transistor and behavioural-levels due to the greater simulation time of the implemented design. ADC’s dynamic performance has been evaluated using various experiments and simulations. Overall, the simulation experiments showed that the design was found to reach an ENOB of 4.9-bit at 572 MHz speed of sample per second, when a 120 MHz analog signal is applied. The achieved peak performance of the design was a SNR of 40 dB, SFDR of 34 dB and an SNDR of 31 dB over a 120 MHz BW at a 1 V supply voltage. Without any complex building blocks, this VCO-based all-digital ADC design provided a key feature of inherent noise shaping property and also found to be well compatible at the deep submicron region.