Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.<p>In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. <p>The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter.

Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.<p>In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. <p>The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter.

A tendência mundial em torno de sistemas SoC – System on Chip – baseados em processo CMOS – Complementary Metal Oxide Semiconductor – digital, apresenta cada vez mais desafios aos projetistas de circuitos integrados. Em especial se observa que enquanto os projetistas de circuitos digitais podem contar com bibliotecas cada vez mais completas de células digitais semi-prontas e ferramentas cada vez mais poderosas para o aprimoramento do projeto, os projetistas analógicos não contam com tais facilidades, sendo necessário realizar o projeto de novas células analógicas para cada especificação recebida. Este trabalho apresenta uma contribuição para a automatização do projeto de blocos analógicos e, para isso, foi escolhido um bloco essencial em muitos projetos analógicos: o amplificador operacional – ampOp. A idéia inicial por trás dessa escolha foi um conjunto de especificações fornecido pela empresa Freescale Semiconductors, para o projeto um préamplificador de áudio realizado no âmbito do Programa Nacional de Microeletrônica – PNM. A topologia escolhida para o amplificador operacional, retirada de [1], foi analisada e utilizada para projeto do amplificador para áudio. Além disso, um software de auxílio ao projeto para este amplificador foi escrito em linguagem C, e seu objetivo é auxiliar no reprojeto do ampOp para atender à especificações diversas. Para isso o software recebe como entradas as próprias especificações e um primeiro projeto do ampOp, realizado com equações simplificadas de projeto. O software então, em conjunto com um simulador elétrico, reprojeta o amplificador, retirando alguns parâmetros relevantes dos arquivos de simulação e utilizando equações de projeto mais completas. Ao final do trabalho, um exemplo de ampOp foi fabricado e caracterizado, sendo os resultados obtidos analisados. / The world trend towards SoC – System on Chip – based on digital CMOS – Complementary Metal Oxide Semiconductor – process presents more and more challenges to the IC designer. One can observe that while digital designers may rely on digital core libraries that are more and more complete, and design tools that are increasingly powerful and capable of optimizing the digital design, analog designers do not have such privileges available, becoming necessary to design such analog cores each time a new set of specifications is received. This work presents a contribution to the automatization of the design of analog cores and, in order to do that, an essential core was chosen: the operational amplifier. The choice for the operational amplifier was made in order to attend to a set of specifications provided by Freescale Semiconductors. This set was applied in the design of an audio pre-amplifier performed in the scope of the National Microelectronics Program – PNM. A topology chosen for the amplifier, extracted from [1], was analysed and applied to design the audio pre-amplifier. Additionaliy, a software for this specific amplifier was written, and its goal is to aid the redesign of the amplifier to comply with a set of specifications. In order to do this, the software receives, as input parameters, the set of specifications and the results of a first amplifier design, done by the analog designer using simplified equations. Then, together with an electrical simulator, the software redesigns the amplifier, reading some relevant information from the output file of the simulation and using more complete relations. At the end of this work, an example of amplifier was manufactured and characterized, and the final results were analyzed.

A tendência mundial em torno de sistemas SoC – System on Chip – baseados em processo CMOS – Complementary Metal Oxide Semiconductor – digital, apresenta cada vez mais desafios aos projetistas de circuitos integrados. Em especial se observa que enquanto os projetistas de circuitos digitais podem contar com bibliotecas cada vez mais completas de células digitais semi-prontas e ferramentas cada vez mais poderosas para o aprimoramento do projeto, os projetistas analógicos não contam com tais facilidades, sendo necessário realizar o projeto de novas células analógicas para cada especificação recebida. Este trabalho apresenta uma contribuição para a automatização do projeto de blocos analógicos e, para isso, foi escolhido um bloco essencial em muitos projetos analógicos: o amplificador operacional – ampOp. A idéia inicial por trás dessa escolha foi um conjunto de especificações fornecido pela empresa Freescale Semiconductors, para o projeto um préamplificador de áudio realizado no âmbito do Programa Nacional de Microeletrônica – PNM. A topologia escolhida para o amplificador operacional, retirada de [1], foi analisada e utilizada para projeto do amplificador para áudio. Além disso, um software de auxílio ao projeto para este amplificador foi escrito em linguagem C, e seu objetivo é auxiliar no reprojeto do ampOp para atender à especificações diversas. Para isso o software recebe como entradas as próprias especificações e um primeiro projeto do ampOp, realizado com equações simplificadas de projeto. O software então, em conjunto com um simulador elétrico, reprojeta o amplificador, retirando alguns parâmetros relevantes dos arquivos de simulação e utilizando equações de projeto mais completas. Ao final do trabalho, um exemplo de ampOp foi fabricado e caracterizado, sendo os resultados obtidos analisados. / The world trend towards SoC – System on Chip – based on digital CMOS – Complementary Metal Oxide Semiconductor – process presents more and more challenges to the IC designer. One can observe that while digital designers may rely on digital core libraries that are more and more complete, and design tools that are increasingly powerful and capable of optimizing the digital design, analog designers do not have such privileges available, becoming necessary to design such analog cores each time a new set of specifications is received. This work presents a contribution to the automatization of the design of analog cores and, in order to do that, an essential core was chosen: the operational amplifier. The choice for the operational amplifier was made in order to attend to a set of specifications provided by Freescale Semiconductors. This set was applied in the design of an audio pre-amplifier performed in the scope of the National Microelectronics Program – PNM. A topology chosen for the amplifier, extracted from [1], was analysed and applied to design the audio pre-amplifier. Additionaliy, a software for this specific amplifier was written, and its goal is to aid the redesign of the amplifier to comply with a set of specifications. In order to do this, the software receives, as input parameters, the set of specifications and the results of a first amplifier design, done by the analog designer using simplified equations. Then, together with an electrical simulator, the software redesigns the amplifier, reading some relevant information from the output file of the simulation and using more complete relations. At the end of this work, an example of amplifier was manufactured and characterized, and the final results were analyzed.

CMOS technology scaling has resulted in reduced supply voltage and intrinsic voltage gain of the transistor. This presents challenges to the analog circuit designers due to lower signal swing and achievable signal to noise ratio (SNR), leading to increased power consumption. At the same time, device speed has increased in lower design nodes, which has not been directly beneficial for analog circuit design. This thesis presents voltage-domain and time-domain circuit scaling friendly circuit architectures that minimize the power consumption and benefit from the increasing transistor speeds. In the voltage-domain, an on-the-fly gain selection block is demonstrated as an alternative to the traditional MDAC architecture to enhance the input dynamic range of a medium-resolution medium-speed analog-to-digital converter (ADC) at reduced supply voltages. The proposed design also eliminates the need for a reference buffer, thus providing power savings. The measured prototype enhances the input dynamic range of a 12bit, 40MSPS ADC to 80.6dB at 1.2V supply voltage. In the time-domain, a generic circuit design approach is presented, followed by an in-depth analysis of Voltage-Controlled-Oscillator based Operational Transconductance Amplifiers (VCO-OTAs). A discrete-time-domain small-signal model based on the zero crossings of the internal VCOs is developed to predict the stability, the step response, and the frequency response of the circuit when placed in feedback. The model accurately predicts the circuit behavior for an arbitrary input frequency, even as the VCO free-running frequency approaches the unity-gain bandwidth of the closed-loop system, where other intuitive small-signal models available in the literature fail. Next, we present an application of VCO-OTA in designing a baseband trans-impedance amplifier (TIA) for current-mode receivers as a scaling-friendly and power-efficient alternative to the inverter-based OTA. We illustrate a design methodology for the choice of the VCO-OTA parameters in the context of a receiver design with an example of a 20MHz RF-channel-bandwidth receiver operating at 2GHz. Receiver simulation results demonstrate an improvement of up to 12dB in blocker 1dB compression point (B1dB) for slightly higher power consumption or up to 2.6x power reduction of the TIA resulting in up to 2x power reduction of the receiver for similar B1dB performance. Next, we present some examples of VCO-OTAs. We first illustrate the benefit of a VCO-OTA in a low-dropout-voltage regulator to achieve a dropout voltage of only100mV and operating down to 0.8V input supply, compared to the prototype based on traditional OTA with a minimum dropout voltage of 150mV, operating at a minimum of 1.2V supply. Both the capacitor-less prototypes can drive up to 1nF load capacitor and provide a current of 60mA. The next prototype showcases a method to reduce the power consumption of a VCO-OTA and spurs at the VCO frequency, with an application in the design of a fourth-order Butterworth filter at 4MHz. The thesis concludes with a design example of 0.2V VCO-OTA.

Digital imaging systems for medical applications use amorphous silicon thin-film transistor (TFT) technology due to its ability to be manufactured over large areas, making it useful for X-ray imaging, which requires imagers to be the size of the subject, unlike optical imaging. TFT technology is used to make imaging arrays coated with an X-ray detector called amorphous selenium (a-Se), which can be grown easily over large areas by being evaporated on a substrate. However, TFT technology is far inferior to crystalline silicon CMOS technology in terms of the speed, stability, noise susceptibility, and feature size. Where CMOS technology falls short is its inability to be manufactured in large wafers at a competitive cost, allowing TFT technology to continue to be dominant in the medical imaging field, unlike the optical imaging industry. This work investigates the feasibility of integrating an imaging array fabricated in CMOS technology with an a-Se detector. The design of a CMOS passive pixel sensor (PPS) array is presented, in addition to how it is integrated with the amorphous selenium detector. Results show that the integrated Selenium-CMOS PPS array has good responsivity to optical light and X-rays, leaving the door open for further research on implementing CMOS imaging architectures going forward. Demonstrating that the PPS chips using CMOS technology can use a-Se as a detector is thus the first step in a promising path of research which should yield substantial and exciting results for the field. Though area may still prove challenging, larger CMOS wafers can be manufactured and tiled to allow for a large enough size for certain diagnostic imaging applications and potentially even large area applications like digital mammography.

Digital imaging systems for medical applications use amorphous silicon thin-film transistor (TFT) technology due to its ability to be manufactured over large areas, making it useful for X-ray imaging, which requires imagers to be the size of the subject, unlike optical imaging. TFT technology is used to make imaging arrays coated with an X-ray detector called amorphous selenium (a-Se), which can be grown easily over large areas by being evaporated on a substrate. However, TFT technology is far inferior to crystalline silicon CMOS technology in terms of the speed, stability, noise susceptibility, and feature size. Where CMOS technology falls short is its inability to be manufactured in large wafers at a competitive cost, allowing TFT technology to continue to be dominant in the medical imaging field, unlike the optical imaging industry. This work investigates the feasibility of integrating an imaging array fabricated in CMOS technology with an a-Se detector. The design of a CMOS passive pixel sensor (PPS) array is presented, in addition to how it is integrated with the amorphous selenium detector. Results show that the integrated Selenium-CMOS PPS array has good responsivity to optical light and X-rays, leaving the door open for further research on implementing CMOS imaging architectures going forward. Demonstrating that the PPS chips using CMOS technology can use a-Se as a detector is thus the first step in a promising path of research which should yield substantial and exciting results for the field. Though area may still prove challenging, larger CMOS wafers can be manufactured and tiled to allow for a large enough size for certain diagnostic imaging applications and potentially even large area applications like digital mammography.

This thesis explores the design and applications of subharmonic mixers in CMOS microwave integrated circuits. First, a 2x down-converting subharmonic mixer is demonstrated with a measured conversion gain of 8 dB using a 2.1 GHz RF signal. Extending the concept of the 2x subharmonic mixer, a 4x subharmonic mixer is proposed that operates in the 12 GHz Ku-band. This circuit is the first 4x subharmonic mixer in CMOS, and achieves a 6 dB conversion gain, which is the highest for any 4x subharmonic mixer regardless of circuit topology or fabrication technology. Furthermore, it achieves very high measured isolation between its ports (e.g. 4LO-RF: 59 dB). Since both the 2x and the 4x subharmonic mixers require a quadrature oscillator, a new oscillator circuit is presented that could be used with either of the aforementioned mixers. This quadrature oscillator uses active superharmonic coupling to establish the quadrature fundamental relationship. The oscillation frequency is 3.0 GHz and the measured output power is -6 dBm. A dual-band mixer/oscillator is also demonstrated that can operate as either a fundamental mixer or a subharmonic mixer depending on a control voltage. This circuit operates from 5.0 GHz to 6.0 GHz or from 9.8 GHz to 11.8 GHz by using either the fundamental output or the second harmonic output of the quadrature oscillator circuit described above and achieves conversion gain over both frequency bands. A novel frequency tripler circuit is presented based on a subharmonic mixer. This circuit uses the 2x subharmonic mixer discussed above, along with a feedforward fundamental cancellation circuit. The measured fundamental suppression is up to 30 dB and the conversion gain is up to 3 dB. Finally, a frequency divider circuit based on a subharmonic mixer is presented that divides the input signal frequency by a factor of three. This circuit uses a single-balanced version of the 2x subharmonic mixer described above in a regenerative divider topology. The measured input signal bandwidth is 300 MHz (5.2 GHz to 5.5 GHz) with an input power of -7 dBm and the maximum conversion gain is 0 dB. / Thesis (Ph.D, Electrical & Computer Engineering) -- Queen's University, 2009-03-24 16:08:31.805

In this work, a programmable frequency divider suitable for millimeter wave phase-lock loops is presented. The frequency divider has been implemented in a 90 nm standard CMOS technology. To the extent of maximizing the operative input frequency, the higher frequency digital blocks of the frequency divider have been realized using dynamic precharge-evaluation logic. Moreover, a non-conventional method to implement non-power-of-2 division ratios has been used for the higher frequency divider stages (input stages).

O presente trabalho tem por objetivo fornecer o embasamento teórico para o projeto de um amplificador de baixo ruído (LNA – Low Noise Amplifier) em tecnologia CMOS que opere em mais de uma faixa de frequência, de modo a permitir seu uso em receptores multibanda e de banda larga. A base teórica que este trabalho abrange desde a revisão bibliográfica do assunto em questão, passando pela análise dos modelos de transistores para alta-frequência, pelo estudo das especificações deste bloco e das métricas utilizadas em projetos de circuitos integrados de RF, bem como pela revisão de topologias clássicas existentes. Com os conhecimentos acima adquiridos, foi possível realizar o projeto de um LNA diferencial de banda larga utilizando tecnologia CMOS IBM 130nm, o qual pode ser aplicado ao padrão IEEE 802.22 para rádios cognitivos (CR). O projeto é baseado na técnica de cancelamento de ruído, sendo validado após apresentar efetiva redução de figura de ruído para banda de frequência desejada, com moderado consumo de potência e utilização moderada de área de silício, devido a solução sem o uso de indutores. O LNA banda larga opera em frequências de 50Mhz a 1GHz e apresenta uma figura de ruído abaixo de 4dB, em 90% da faixa, um ganho acima de 12dB, e perda de retorno na entrada e na saída maiores que 12dB. O IIP3 e a frequência de ocorrência de compressão a 1dB com a entrada em 580MHz estão acima de 0dBm e -10dBm respectivamente. Possui consumo de 46,5mWpara fonte de 1,5V e ocupa uma área ativa de apenas 0,28mm x 0,2mm. / This work presents the theoretical basis for the design of a low noise amplifier (LNA) in CMOS technology that operates in more than one frequency band, which enables its use in multi-band and wideband receivers. The theoretical basis that this work will address extends from the literature review on the subject, through the analysis of models of MOS transistors for high frequencies, study of specifications of this block and the metrics used in RF integrated circuit design, as well as the review of existing classical LNA topologies. Based on the knowledge acquired above, the design of a differential wideband LNA is developed using IBM 130nm RF CMOS process, which can be used in IEEE 802.22 Cognitive Radio (CR) applications. The design is based on the noise-canceling technique, with an indutctorless solution, showing that this technique effectively reduces the noise figure over the desired frequency range with moderate power consumption and a moderate utilization of silicon die area. The wideband LNA covers the frequency range from 50 MHz to 1 GHz, achieving a noise figure below 4dB in over 90% of the band of interest, a gain of 11dB to 12dB, and an input/output return loss higher than -12 dB. The input IIP3 and input P1dB at 580MHz are above 0dB and -10dB, respectively. It consumes 46.5mW from a 1.5V supply and occupies an active area of only 0.056mm2 (0.28mm x 0.2mm).