Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.<p>In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. <p>The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter.

Quadrature digital modulation techniques are widely used in modern communication systems because of their high performance and flexibility. However, these advantages come at the cost of high power consumption. As a result, power consumption has to be taken into account as a main design factor of the modulator.<p>In this thesis, a low-power quadrature digital modulator in 0.18um CMOS is presented with the target system clock speed of 150 MHz. The quadrature digital modulator consists of several key blocks: quadrature direct digital synthesizer (QDDS), pulse shaping filter, interpolation filter and inverse sinc filter. The design strategy is to investigate different implementations for each block and compare the power consumption of these implementations. Based on the comparison results, the implementation that consumes the lowest power will be chosen for each block. First of all, a novel low-power QDDS is proposed in the thesis. Power consumption estimation shows that it can save up to 60% of the power consumption at 150 MHz system clock frequency compared with one conventional design. Power consumption estimation results also show that using two pulse shaping blocks to process I/Q data, cascaded integrator comb (CIC) interpolation structure, and inverse sinc filter with modified canonic signed digit (MCSD) multiplication consume less power than alternative design choices. These low-power blocks are integrated together to achieve a low-power modulator. The power consumption estimation after layout shows that it only consumes about 95 mW at 150 MHz system clock rate, which is much lower than similar commercial products. <p>The designed modulator can provide a low-power solution for various quadrature modulators. It also has an output bandwidth from 0 to 75 MHz, configurable pulse shaping filters and interpolation filters, and an internal sin(x)/x correction filter.

This research aims to design and implement GaAs HBT MMICs for the two crucial components in W-CDMA transmitters, quadrature modulator and upconverter, with thorough evaluation of the package and PCB effects. To construct a strong theoretical foundation, the small-signal modeling of HBTs and the EM-characterization of package and PCB interconnects are intensively studied. In this dissertation, a novel extrinsic-inductance independent approach is developed for direct extraction of the intrinsic elements in a hybrid-pi equivalent circuit of HBTs. The interconnects of leadless RFIC packages and test PCBs are investigated using the 3-D EM simulation tools and transformed into the equivalent circuits for co-analysis with the designed HBT MMICs. The first HBT MMIC design is a W-CDMA direct-conversion quadrature modulator incorporating a new 90 degrees phase shifter. Although the proposed 90 degrees phase shifter has a remarkable advantage over the others in implementation loss, it is rather susceptible to the package and PCB effects, resulting in a moderate degradation of EVM. The second HBT MMIC design is a W-CDMA upconverter incorporating a popular micromixer. Although the micromixer-based upconverter consumes much less current at low output powers to achieve the same high linearity when compared to a Gilbert mixer-based design, it is quite susceptible to the package and PCB effects, causing a significant degradation in ACPR. Comparison between theory and measurement shows good agreement in evaluating the influences of package and PCB interconnects on both HBT MMICs.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / When designing transmitters for quadrature modulation schemes, the designer always tries to achieve good balance and symmetry of the in-phase (I) and quadrature (Q) branches of the modulator in terms of amplitude, phase, and offsets. Perfect balance between modulators is ideal but rarely if ever achieved. The Advance Range Telemetry (ARTM) program has placed indirect specifications on the remnant carrier and sideband levels which are controlled by modulator imbalance. These specifications will govern the ARTM programs first generation of Feher’s patented quadrature phase shift keying, version B (FQPSK-B) [9] airborne telemetry transmitters. The ARTM Program has also adopted test procedures for quantifying these modulation imbalances. This paper looks at the effects of modulator imbalances on spectral occupancy and bit error probability of the airborne telemetry link. It also outlines how these imbalances influence the levels in one of the ARTM specifications. Recommendations are presented based on the measured data for higher bit rate telemetry systems.

This thesis researchs the design of quadrature modulator consists of 120MHz quadrature modulator that is fabricated using hybrid elements and print circuit board (PCB) technology for digital signal generator and quadrature modulator monolithic-microwave integrated-circuit (MMIC) that is fabricated using GaAs heterojunction bipolar transistor (HBT) technology for Personal Communication Service (PCS) applications. The 120MHz quadrature modulator incorporates power divider/combiner, phase shifter and doubly balanced mixer; the design architecture, principle and measurement results of division are presented in this thesis. A quadrature modulator is implemented by combining every division and measures specifications accurately, comparing with that of Agilent ESG-D series digital signal generator with the same carrier frequency and digital modulation. The quadrature modulator MMIC for PCS applications incorporates phase shifter, Gilbert cell mixer, differential to single-ended converter and RF amplifier at output; the design architecture, principle and simulation results of division are presented in this thesis. A quadrature modulator is integrated by combining every division and simulates parameters strictly.For troublesome specification measurement of quadrature modulator, this thesis also presents measurement method and instrument setup detailedly.