abstract: Semiconductor devices are generally analyzed with relatively simple equations or with detailed computer simulations. Most text-books use these simple equations and show device diagrams that are frequently very simplified and occasionally incorrect. For example, the carrier densities near the pinch-off point in MOSFETs and JFETs and the minority carrier density in the base near the reverse-biased base-collector junction are frequently assumed to be zero or near zero. Also the channel thickness at the pinch-off point is often shown to approach zero. None of these assumptions can be correct. The research in thesis addresses these points. I simulated the carrier densities, potentials, electric fields etc. of MOSFETs, BJTs and JFETs at and near the pinch-off regions to determine exactly what happens there. I also simulated the behavior of the quasi-Fermi levels. For MOSFETs, the channel thickness expands slightly before the pinch-off point and then spreads out quickly in a triangular shape and the space-charge region under the channel actually shrinks as the potential increases from source to drain. For BJTs, with collector-base junction reverse biased, most minority carriers diffuse through the base from emitter to collector very fast, but the minority carrier concentration at the collector-base space-charge region is not zero. For JFETs, the boundaries of the space-charge region are difficult to determine, the channel does not disappear after pinch off, the shape of channel is always tapered, and the carrier concentration in the channel decreases progressively. After simulating traditional sized devices, I also simulated typical nano-scaled devices and show that they behave similarly to large devices. These simulation results provide a more complete understanding of device physics and device operation in those regions usually not addressed in semiconductor device physics books. / Dissertation/Thesis / M.S. Electrical Engineering 2011

The master’s thesis focuses on model designing of active components for PSpice simulator. Creation of models are based on text description, which is avaible in Cadence Spectre libraries. The aim of this thesis is approximate conversion of CMOS and bipolar tranzistors based on I3T 0.35 m technology. Simulation’s results and their comparation are discussed below.

There are many kinds of commercial memory cards on the market. Due to great improvements in modern technology, they have great amounts of capacity, low power consumption, and are easily available. Therefore a data logging system using a commercial memory card is a convenient and economic procedure. This thesis introduces a wearable data logging system for physiological recording. A front-end amplifier, analog to digital converter, and a memory card controller compose the basis of this system. The front-end amplifier uses a switched-capacitor structure, so the output waveform is discrete in regard to the time domain. This brings an advantage in saving power for not keeping charging the load capacitance. Lateral bipolar transistors fabricated in a CMOS process are used as input devices. A conventional ADC is used to convert the amplified signal into digital data. Finally MultiMediaCard is chosen as a large storage space. This thesis contributes the analysis, design and measurement of the amplifier front-end. In addition, the design and implementation of a controller circuit for sequential data storage into the MultiMediaCard memory is described. Special attention was paid to achieving a small area, low-complexity and low-power implementation suitable for integration. Measured results obtained from a preliminary FPGA implementation are reported and the functionality of a complete logger circuit is demonstrated with measured results.

Integrated temperature sensors play an important role in enhancing the performance of on-chip power and thermal management systems in today's highly-integrated system-on-chip (SoC) platforms, such as microprocessors. Accurate on-chip temperature measurement is essential to maximize the performance and reliability of these SoCs. However, due to non-uniform power consumption by different functional blocks, microprocessors have fairly large thermal gradient (and variation) across their chips. In the case of multi-core microprocessors for example, there are task-specific thermal gradients across different cores on the same die. As a result, multiple temperature sensors are needed to measure the temperature profile at all relevant coordinates of the chip. Subsequently, the results of the temperature measurements are used to take corrective measures to enhance the performance, or save the SoC from catastrophic over-heating situations which can cause permanent damage. Furthermore, in a large multi-core microprocessor, it is also imperative to continuously monitor potential hot-spots that are prone to thermal runaway. The locations of such hot spots depend on the operations and instruction the processor carries out at a given time. Due to practical limitations, it is an overkill to place a big size temperature sensor nearest to all possible hot spots. Thus, an ideal on-chip temperature sensor should have minimal area so that it can be placed non-invasively across the chip without drastically changing the chip floor plan. In addition, the power consumption of the sensors should be very low to reduce the power budget overhead of thermal monitoring system, and to minimize measurement inaccuracies due to self-heating. The objective of this research is to design an ultra-small size and ultra-low power temperature sensor such that it can be placed in the intimate proximity of all possible hot spots across the chip. The general idea is to use the leakage current of a reverse-bias p-n junction diode as an operand for temperature sensing. The tasks within this project are to examine the theoretical aspect of such sensors in both Silicon-On-Insulator (SOI), and bulk Complementary Metal-Oxide Semiconductor (CMOS) technologies, implement them in deep sub-micron technologies, and ultimately evaluate their performances, and compare them to existing solutions. / text

No description available.

In order to correctly perform circuit simulation, it is crucial that parasitic capacitances near devices are accurately extracted and are consistent with the SPICE models. Although 3D device simulation can be used to extract such parasitics, it is expensive and does not consider the effects of nearby interconnect and devices in a layout. Conventional rule-based layout parasitic extraction (LPE) tools which are used for interconnect extraction are inaccurate in modeling 3D effects near devices. In this thesis, we propose a methodology which combines 3D field solver based extraction with the ability to exclude specific parasitics from among the parameters in the SPICE model. We use this methodology to extract parasitics due to fringing fields and sidewall capacitances in MOSFETs, bipolar transistors and FinFETs in advanced process nodes. We analyze the importance of considering layout and process variables in device extraction by comparing with standard SPICE models. The results are validated by circuit simulation using predictive technology models and test chips. We also demonstrate the versatility of this flow by modeling the capacitance contributions of the raised gate profile in nanoscale FinFETs.

The object of this thesis is to explore the low-frequency noise (LFN) in silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and lateral bipolar junction transistors (BJTs). The LFN of SiGe HBTs and lateral BJTs not only determines the lowest detectable signal limit but also induces phase noise in high-frequency applications. Characterizing the LFN behavior and understanding the physical noise mechanism, therefore, are very important to improve the device and circuit performance. The dissertation achieves the object by investigating the LFN of SiGe HBTs and lateral BJTs with different structures for performance optimization and radiation tolerance, as well as by building models that explain the physical mechanism of LFN in these advance bipolar technologies. The scope of this research is separated into two main parts: the LFN of SiGe HBTs; and the LFN of lateral BJTs. The research in the LFN of SiGe HBTs includes investigating the effects of interfacial oxide (IFO), temperature, geometrical dimensions, and proton radiation. It also includes utilizing physical models to probe noise mechanisms. The research in the LFN of lateral BJTs includes exploring the effects of doping and geometrical dimensions. The research work is envisioned to enhance the understanding of LFN in SiGe HBTs and lateral BJTs.

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第16862号 / 工博第3583号 / 新制||工||1541(附属図書館) / 29537 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 藤田 静雄, 准教授 浅野 卓 / 学位規則第4条第1項該当

The work in this dissertation presents the first attempt in the literature to propose the concept of "soft switch". The goal of "soft switch" is to develop a standard PWM switch cell with built-in adaptive soft switching capabilities. Just like a regular switch, only one PWM signal is needed to drive the soft switch under soft switching condition. The core technique in soft switch development is a built-in adaptive soft switching circuit with minimized circulation energy. The necessity of minimizing circulation energy is first analyzed. The design and implementation of a universal controller for implementation of variable timing control to minimize circulation energy is presented. The controller has been tested successfully with three different soft switching inverters for electric vehicles application in the Partnership for a New Generation Vehicles (PNGV) project. To simplify the control, several methods to achieve soft switching with fixed timing control are proposed by analyzing a family of zero-voltage switching converters. The driver based soft switch concept was originated from development of a base driver circuit for current driven bipolar junction transistor (BJT). A new insulated-gate-bipolar-transistor (IGBT) and power metal-oxide-semiconductor field-effect-transistor (MOSFET) gated transistor (IMGT) base drive structure was initially proposed for a high power SiC BJT. The proposed base drive method drives SiC BJTs in a way similar to a Darlington transistor. With some modification, a new base driver structure can adaptively achieve zero voltage turn-on for BJT at all load current range with one single gate. The proposed gate driver based soft switching method is verified by experimental test with both Si and SiC BJT. The idea is then broadened for "soft switch" implementation. The whole soft switched BJT (SSBJT) structure behaves like a voltage-driven soft switch. The new structure has potentially inherent soft transition property with reduced stress and switching loss. The basic concept of the current driven soft switch is then extended to a voltage-driven device such as IGBT and MOSFET. The key feature and requirement of the soft switch is outlined. A new coupled inductor based soft switching cell is proposed. The proposed zero-voltage-transition (ZVT) cell serves as a good candidate for the development of soft switch. The "Equivalent Inductor" and state plane based analysis method are used to simply the analysis of coupled inductor based zero-voltage switching scheme. With the proposed analysis method, the operational property of the ZVT cell can be identified without solving complicated differential equations. Detailed analysis and design is proposed for a 3kW boost converter example. With the proposed soft switch design, the boost converter can achieve up to 98.9% efficiency over a wide operation range with a single gate drive. A high power inverter with coupled inductor scheme is also designed with simple control compared to the earlier implementation. A family of soft-switching converters using the proposed "soft switch" cell can be developed by replacing the conventional PWM switch with the proposed soft switch. / Ph. D.

This thesis provides insight into state-of-the-art 1.2 kV silicon carbide (SiC) power semiconductor transistors, including the MOSFET, BJT, SJT, and normally-on and normally-off JFETs. Both commercial and sample devices from the semiconductor industry's well-known manufacturers were evaluated in this study. These manufacturers include: Cree Inc., ROHM Semiconductor, General Electric, Fairchild Semiconductor, GeneSiC Semiconductor, Infineon Technologies, and SemiSouth Laboratories. To carry out this work, static characterization of each device was performed from 25 ºC to 200 ºC. Dynamic characterization was also conducted through double-pulse tests. Accordingly, this thesis describes the experimental setup used and the different measurements conducted, which comprise: threshold voltage, transconductance, current gain, specific on-resistance, parasitic capacitances, internal gate resistance, and the turn on and turn off switching times and energies. For the latter, the driving method used for each device is described in detail. Furthermore, for the devices that require on-state dc currents, driving losses are taken into consideration. While all of the SiC transistors characterized in this thesis demonstrated low specific on-resistances, the SiC BJT showed the lowest, with Fairchild's FSICBH057A120 SiC BJT having 3.6 mΩ•cm2 (using die area) at 25 ºC. However, the on-resistance of GE's SiC MOSFET proved to have the smallest temperature dependency, increasing by only 59 % from 25 ºC to 200 ºC. From the dynamic characterization, it was shown that Cree's C2M0080120D second generation SiC MOSFET achieved dv/dt rates of 57 V/ns. The SiC MOSFETs also featured low turn off switching energy losses, which were typically less than 70 µJ at 600 V bus voltage and 20 A load current. / Master of Science