The superior characteristics of silicon carbide, compared with silicon, have suggested considering this material for the next generation of power semiconductor devices. Among the different power switches, the bipolar junction transistor (BJT) can provide a very low forward voltage drop, a high current capability and a fast switching speed. However, in order to compete on the market, it is crucial to a have high current gain and a breakdown voltage close to ideal. Moreover, the absence of conductivity modulation and long-term stability has to be solved. In this thesis, these topics are investigated comparing simulations and measurements. Initially, an efficient etched JTE has been simulated and fabricated. In agreement with the simulations, the fabricated diodes exhibit the highest BV of around 4.3 kV when a two-zone JTE is implemented. Furthermore, the simulations and measurements demonstrate a good agreement between the electric field distribution inside the device and the optical luminescence measured at breakdown. Additionally, an accurate model to simulate the forward characteristics of 4H-SiC BJTs is presented. In order to validate the model, the simulated current gains are compared with measurements at different temperatures and different base-emitter geometries. Moreover, the simulations and measurements of the on-resistance are compared at different base currents and different temperatures. This comparison, coupled with a detailed analysis of the carrier concentration inside the BJT, indicates that internal forward biasing of the base-collector junction limits the BJT to operate at high current density and low forward voltage drop simultaneously. In agreement with the measurements, a design with a highly-doped extrinsic base is proposed to alleviate this problem. In addition to the static characteristics, the comparison of measured and simulated switching waveforms demonstrates that the SiC BJT can provide fast switching speed when it acts as a unipolar device. This is crucial to have low power losses during transient. Finally, the long-term stability is investigated. It is observed that the electrical stress of the base-emitter diode produces current gain degradation; however, the degradation mechanisms are still unclear. In fact, the analysis of the measured Gummel plot suggests that the reduction of the carrier lifetime in the base-emitter region might be only one of the causes of this degradation. In addition, the current gain degradation due to ionizing radiation is investigated comparing the simulations and measurements. The simulations suggest that the creation of positive charge in the passivation layer can increase the base current; this increase is also observed in the electrical measurements. / QC 20120522

This work investigates the effects of post-fabrication applied mechanical tensile strain on Silicon (Si) Bipolar Junction Transistor (BJT) and Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices. Applied strain effects on MOSFET transistors are being heavily explored, both in academia and industry, as a possible alternative to dimensional scaling. This thesis focuses on how strain affects Si BJT and SiGe HBTs, where tensile strain is applied after the Integrated Circuit (IC) fabrication has been completed, using a unique mechanical method. The consequence of both biaxial and uniaxial strain application has been examined in this work. Chapter I gives a short introduction to the scope of this work, the motivation for conducting this research and the contributions of this experiment. Chapter II entails a brief discussion on Si bipolar and SiGe heterojunction bipolar device physics, which are key to the understanding of strain induced effects. Chapter III provides a thorough summary of the current state of research regarding applied strain, also known as Strain Engineering. It covers different types, orientations, and application techniques of strain. Chapter IV, highlights the details of this experiment, and also presents the measured results. It is observed that for this particular method of biaxial tensile strain application, the collector current (IC) and current gain degrades for both Si BJT and SiGe HBT. Base current (IB) decreases in Si BJT, though it increases for SiGe HBT after strain. Little or no change is noticed in the dynamic or ac small-signal characteristics like unity-gain cutoff frequency (fT) and base resistance (rBB) after strain. Uniaxially strained SiGe HBT samples showed similar results as the biaxial strain. This chapter also attempts to explain the origin of these strain induced changes. Chapter V, summarizes the finding of this experiment, and concludes the thesis with some future directions for this research.

This research thesis seeks to investigate a new method to sense the classical Hall effect in Hall devices under the influence of a magnetic field primarily manufactured in complementary metal oxide semiconductor (CMOS) technologies. The thesis poses a research question enabling the investigation into whether or not the geometrical factor in a classical Hall device can be improved by proposing a new method to sense the Hall effect indirectly in standard CMOS technology. State of the art Hall effect devices rely on low ohmic contacts to sense the Hall voltage effect. These contacts along with the geometry can have an adverse effect on the Hall device sensitivity. Furthermore, the Hall voltage in Silicon can be very limited in comparison to high mobility semiconductor materials. It was found that by replacing the highly doped n-type sensing contacts of the Hall device with highly doped p-type contacts, a vertical bipolar junction transistor could be formed. This transistor, normally considered a parasitic element, ultimately leads to a very useful sensing technique in which the Hall current is sensed and amplified by the transistor forward gain, β + 1. The Hall effect appears as a current through the emitter of the transistor. The major contribution of this research resides in a novel method to measure as well as amplify the Hall effect in a square n-well plate manufactured on a standard CMOS technology. The research also bridges the gap found in literature on the subject of direct versus indirect Hall sensing techniques. The outcome of the research also addresses practical implementations of such alternate methods as well as the effect the methods have on fundamental noise limits and differences in noise between the proposed method and traditional methods. The device although not improving the fundamental geometrical factor of the plate which was found to be dominated by the geometry itself, was proven to be functional as well as behaving according to Hall effect theory. Furthermore, the gain that even low forward gain bipolar transistors contribute to the signal, more than compensates for the loss of Hall effect contributed by the geometrical correction factor. The method also contributes less noise in comparison to typical traditional methods of Hall voltage amplification using operational amplifiers. The proposed method thus allows for a very simple measuring technique that is compatible with standard CMOS technology processes. ## Hierdie navorsings tesis is gemik daarop om 'n nuwe meetmetode te ondersoek om die klassieke Hall effek te meet in Hall toestelle onder die invloed van 'n magneetveld wat primér in komplementêre metaaloksied-halfgeleiertegnologie (CMOS) vervaardig word. Die tesis stel 'n navorsingsvraag wat lei tot die ondersoek van die vraag of die geometriese faktor in 'n klassieke Hall toestel verbeter kan word deur om 'n nuwe metode voor te stel om die Hall effek indirek te meet in standaard CMOS tegnologie. Nuutste navorsing oor meetmetodes in Hall effek toestelle, maak nog steeds staat op lae ohmiese kontakte om die Hall spanning effek te meet. Hierdie kontakte saam met die meetkunde van die toestel, het 'n nadelige uitwerking op die Hall toestel se sensitiwiteit. Verder is die Hall spanning in Silikon baie beperk met vergelyking tot hoë mobiliteit halfgeleier materiale. Daar is gevind dat deur die vervanging van die hoogs gedoteerde n-tipe meetkontakte van die Hall toestel met hoogs gedoteerde p-tipe kontakte, kan vertikale bipolêre transistors gevorm word. Hierdie transistor, gewoonlik beskou as 'n parasitiese element, lei tot 'n baie nuttige meet tegniek waarin die Hall stroom gemeet en versterk word deur die transistor se voorwaartse wins, β + 1. Die Hall effek verskyn as 'n stroom deur die emittor van die transistor. Die grootste bydrae van hierdie navorsing lê in 'n nuwe metode om die Hall effek in 'n vierkantige n-dam plaat wat in standaard CMOS tegnologie vervaardig is te meet sowel as om die sein te versterk. Die navorsing oorbrug ook die gaping gevind in literatuur oor die onderwerp van direkte teenoor indirekte Hall meet tegnieke. Die uitkoms van die navorsing spreek ook die praktiese implementering van die meetmetode aan sowel as die effek wat die meetmetode op fundamentele ruisgrense en verskille in ruis tussen die voorgestelde meetmetode en tradisionele meetmetodes het. Die toestel, hoewel nie gelei het tot ‘n verbetering van die fundamentele geometriese faktor van die plaat wat oorheers is deur die meetkunde van die plaat self, is wel funksioneel bewys, asook dat dit optree volgens Hall effek teorie. Verder is daar gevind dat die wins wat selfs lae voorwaartse wins bipolêre transistors bydra tot die sein, meer as die verlies wat die meetkundige faktor veroorsaak op die Hall effek kan herwin. Dié meetmetode dra ook minder ruis by met vergelyking tot tipiese tradisionele meetmetodes soos operasionele versterkers, wat vir Hall spanning versterking gebruik word. Die voorgestelde meetmetode skep dus ‘n baie eenvoudige meettegniek wat versoenbaar is met standaard CMOS tegnologie prosesse. / Thesis (PhD)--University of Pretoria, 2014. / lk2014 / Electrical, Electronic and Computer Engineering / PhD / unrestricted

This thesis aims to bring an understanding to the silicon carbide (SiC) bipolar junction transistor (BJT). SiC power devices are superior to the silicon IGBT in several ways. They are for instance, able to operate with higher efficiency, at higher frequencies, and at higher junction temperatures. From a system point of view the SiC power device could decrease the cost and complexity of cooling, reduce the size and weight of the system, and enable the system to endure harsher environments. The three main SiC power device designs are discussed with a focus on the BJT. The SiC BJT is compared to the SiC junction field-effect transistor (JFET) and the metal-oxide semiconductor field-effect transistor (MOSFET). The potential of employing SiC power devices in applications, ranging from induction heating to high-voltage direct current (HVDC), is presented. The theory behind the state-of-the-art dual-source (2SRC) base driver that was presented by Rabkowski et al. a few years ago is described. This concept of proportional base drivers is introduced with a focus on the discretized proportional base drivers (DPBD). By implementing the DPBD concept and building a prototype it is shown that the steady-state consumption of the base driver can be reduced considerably.  The aspects of the reverse conduction of the SiC BJT are presented. It is shown to be of importance to consider the reduced voltage drop over the base-emitter junction. Last the impact of SiC unipolar and bipolar devices in series-resonant (SLR) converters is presented. Two full-bridges are designed and constructed, one with SiC MOSFETs utilizing the body diode for reverse conduction during the dead-time, and the second with SiC BJTs with anti-parallel SiC Schottky diodes. It is found that the SiC power devices, with their absence of tail current, are ideal devices to fully utilize the soft-switching properties that the SLR converters offer. The SiC MOSFET benefits from its possibility to utilize reverse conduction with a low voltage drop. It is also found that the size of capacitance of the snubbers can be reduced compare to state-of-the-art silicon technology. High switching frequencies of 200 kHz are possible while still keeping the losses low. A dead-time control strategy for each device is presented. The dual control (DuC) algorithm is tested with the SiC devices and compared to frequency modulation (FM). The analytical investigations presented in this thesis are confirmed by experimental results on several laboratory prototype converters. / <p>QC 20150529</p>

No description available.

This thesis deals with the main aspects in chemical vapordeposition (CVD) of silicon (Si) and silicon-germanium (Si1-xGex) films for high-speed bipolar transistors.In situdoping of polycrystalline silicon (poly-Si)using phosphine (PH3) and disilane (Si2H6) in a low-pressure CVD reactor was investigated toestablish a poly-Si emitter fabrication process. The growthkinetics and P incorporation was studied for amorphous Si filmgrowth. Hydrogen (H) incorporated in the as-deposited films wasrelated to growth kinetics and the energy for H2desorption was extracted. Film properties such asresistivity, mobility, carrier concentration and grain growthwere studied after crystallization using either furnaceannealing or rapid thermal annealing (RTA). In order tointegrate an epitaxial base, non-selective epitaxial growth(NSEG) of Si and SiGe in a lamp-heated single-waferreduced-pressure CVD reactor was examined. The growth kineticsfor Si epitaxy and poly-Si deposition showed a differentdependence on the deposition conditions i.e. temperature andpressure. The growth rate difference was mainly due to growthkinetics rather than wafer surface emissivity effects. However,it was observed that the growth rate for Si epitaxy and poly-Sideposition was varying during growth and the time-dependencewas attributed to wafer surface emissivity variations. A modelto describe the emissivity effects was established, taking intoconsideration kinetics and the reactor heating mechanisms suchas heat absorption, emission andconduction. Growth ratevariations in opening of different sizes (local loading) andfor different oxide surface coverage (global loading) wereinvestigated. No local loading effects were observed, whileglobal loading effects were attributed to chemical as well astemperature effects. Finally, misfit dislocations formed in theSiGe epitaxy during NSEG were found to originate from theinterface between the epitaxial and polycrystalline regions.The dislocations tended to propagate across the activearea. <b>Keywords:</b>chemical vapor deposition (CVD), bipolarjunction transistor (BJT), heterojunction bipolar transistor(HBT), silicon-germanium (SiGe), epitaxy, poly-Si emitter,in situdoping, non-selective epitaxy (NSEG), loadingeffect, emissivity effect

Silicon carbide bipolar junction transistors (BJTs) are attractive power switching devices because of the unique material properties of SiC with high breakdown electric field, high thermal conductivity and high saturated drift velocity of electrons. The SiC BJT has potential for very low specific on-resistances and this together with high temperature operation makes it very suitable for applications with high power densities. For SiC BJTs the common emitter current gain (β), the specific on-resistance (RSP_ON), and the breakdown voltage are important to optimize for competition with silicon based power devices. In this thesis, power SiC BJTs with high current gain β ≈ 60 , low on-resistance RSP_ON ≈ 5 mΩcm2, and high breakdown voltage BVCEO ≈ 1200 V have been demonstrated. The 1200 V SiC BJT that has been demonstrated has about 80 % lower on-state power losses compared to a typical 1200 V Si IGBT chip. A continuous epitaxial growth of the base-emitter layers has been used to reduce interface defects and thus improve the current gain. A significant influence of surface recombination on the current gain was identified by comparing the experiments with device simulations. In order to reduce the surface recombination, different passivation layers were investigated in SiC BJTs, and thermal oxidation in N2O ambient was identified as an efficient passivation method to increase the current gain. To obtain a low contact resistance, especially to the p-type base contact, is one critical issue to fabricate SiC power BJTs with low on-resistance. Low temperature anneal (~ 800 oC) of a p-type Ni/Ti/Al contact on 4H-SiC has been demonstrated. The contact resistivity on the ion implanted base region of the BJT was 1.3 × 10-4 Ωcm2 after annealing. The Ni/Ti/Al p-type ohmic contact was adapted to 4H-SiC BJTs fabrication indicating that the base contact plays a role for achieving a low on-resistance of SiC BJTs. To achieve a high breakdown voltage, optimized junction termination is important in a power device. A guard ring assisted Junction Termination Extension (JTE) structure was used to improve the breakdown voltage of the SiC BJTs. The highest breakdown voltage of the fabricated SiC BJTs was obtained for devices with guard ring assisted JTE using the base contact implant step for a simultaneous formation of guard rings. As a new approach to fabricate SiC BJTs, epitaxial regrowth of an extrinsic base layer was demonstrated. SiC BJTs without any ion implantation were successfully demonstrated using epitaxial regrowth of a highly doped p-type region and an etched JTE using the epitaxial base. A maximum current gain of 42 was measured for a 1.8 mm × 1.8 mm BJT with a stable and reproducible open base breakdown voltage of 1800 V. / QC 20100819

No description available.

<p>This thesis deals with the main aspects in chemical vapordeposition (CVD) of silicon (Si) and silicon-germanium (Si_1-xGe_x) films for high-speed bipolar transistors.<i>In situ</i>doping of polycrystalline silicon (poly-Si)using phosphine (PH₃) and disilane (Si₂H₆) in a low-pressure CVD reactor was investigated toestablish a poly-Si emitter fabrication process. The growthkinetics and P incorporation was studied for amorphous Si filmgrowth. Hydrogen (H) incorporated in the as-deposited films wasrelated to growth kinetics and the energy for H₂desorption was extracted. Film properties such asresistivity, mobility, carrier concentration and grain growthwere studied after crystallization using either furnaceannealing or rapid thermal annealing (RTA). In order tointegrate an epitaxial base, non-selective epitaxial growth(NSEG) of Si and SiGe in a lamp-heated single-waferreduced-pressure CVD reactor was examined. The growth kineticsfor Si epitaxy and poly-Si deposition showed a differentdependence on the deposition conditions i.e. temperature andpressure. The growth rate difference was mainly due to growthkinetics rather than wafer surface emissivity effects. However,it was observed that the growth rate for Si epitaxy and poly-Sideposition was varying during growth and the time-dependencewas attributed to wafer surface emissivity variations. A modelto describe the emissivity effects was established, taking intoconsideration kinetics and the reactor heating mechanisms suchas heat absorption, emission andconduction. Growth ratevariations in opening of different sizes (local loading) andfor different oxide surface coverage (global loading) wereinvestigated. No local loading effects were observed, whileglobal loading effects were attributed to chemical as well astemperature effects. Finally, misfit dislocations formed in theSiGe epitaxy during NSEG were found to originate from theinterface between the epitaxial and polycrystalline regions.The dislocations tended to propagate across the activearea.</p><p><b>Keywords:</b>chemical vapor deposition (CVD), bipolarjunction transistor (BJT), heterojunction bipolar transistor(HBT), silicon-germanium (SiGe), epitaxy, poly-Si emitter,<i>in situ</i>doping, non-selective epitaxy (NSEG), loadingeffect, emissivity effect</p>

Un nouveau circuit de protection contre les surtensions a été développé. Dans ce circuit de protection, la partie<br />dissipative est monolithiquement intégrée dans la même puce du transistor à protéger avec aucune modification<br />technologique additionnelle. Cette intégration monolithique tire profit du système de refroidissement du<br />transistor à protéger pour le refroidissement de la partie intégrée. En même temps, elle réduit au minimum les<br />problèmes de connections entre le transistor à protéger et son système de protection. En plus, la conception de<br />ce circuit de protection permet d'ajuster le seuil de tension de protection. C'est utile pour la mise en série des<br />transistors pour des applications à haute tension. Un modèle du BJT comme transistor de protection est établi.<br />Ce modèle se distingue des modèles existants car il prend en compte que le BJT fonctionne en mode linéaire.<br />Un modèle thermique de l'ensemble des transistors intégrés évalue le comportement de ces transistors malgré la<br />différence entre leur mode de fonctionnement. Ce modèle donne une meilleure distribution des cellules du<br />transistor de protection dans la puce. Des résultats pratiques à partir des composants MOSFETs autoprotégés<br />que nous avons fabriqués valident la solution proposée. Un démonstrateur de hacheur série utilisant deux<br />MOSFETs autoprotégés en série montre l'efficacité de notre solution.