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Complementary delta-doped AlGaAs/GaAs Heterojunction Field Effect Transistor (CHFET) devices and circuits were fabricated using MBE and a 2�� non-planar gate recess process. Several schemes were used in an attempt to improve the performance of the p-channel HFETs. These included delta-doping, carbon-doping and dipole-doping. Circuits and individual n- and p- channel devices were fabricated on a stacked delta-doped complementary structure. The circuits failed to perform due to complications with adjusting the threshold voltage. However, Individual devices were successfully characterized, p-channel devices with extrinsic transconductances up to 14 mS/mm, n-channel devices with extrinsic transconductances up to 120 mS/mm and a unity power gain bandwidth of 5.5 GHz. / Graduation date: 1995

Graduation date: 1994

published_or_final_version / abstract / toc / Electrical and Electronic Engineering / Master / Master of Philosophy

This work focused on the fabrication and electrical characterization of electronic devices and the applications include the n-channel organic field-effect transistors (OFETs), organic complementary circuits, and the germanium nanowire transistors. In organic devices, carbonyl-functionalized [alpha],[omega]-diperfluorohexyl quaterthiophenes (DFHCO-4T) and N,N' --bis(n-octyl)-dicyanoperylene-3,4:9,10-bis(dicarboximide) (PDI-8CN2) are used as n-type semiconductors. The effect of dielectric/electrode surface treatment on the response of bottom-contact devices was also examined to maximize the device performance. Some of innovative techniques that employ the conducting polymer, poly(3,4-ethylenedioxythiophene) / poly(styrene sulfonate) (PEDOT/PSS) for the fabrication of OFETs, were compared and investigated. The device performance and the fabrication yield were also considered. Organic complementary ring oscillators and D flip-flops were demonstrated with PDI-8CN2 and pentacene as the n-type and ptype material, respectively. Both circuits recorded the highest speed that any organic transistor-based complementary circuit has achieved to date. The speed of these complementary circuits will be enhanced by increasing the mobility of n-channel further as well as reducing channel lengths and overlap capacitances between the source/drain electrodes and the gate. The semiconductors should be solution processible to be compatible with the inexpensive fabrication techniques envisioned for printed electronic circuits. PDI-8CN2 was used for solution-processed n-channel OFETs and the various parameters are compared for the optimization of devices. Utilizing optimized process parameters and surface treatments for solution-deposited PDI-8CN2 OFETs, we have successfully shown the first fabrication of complementary organic ring oscillators and Dflip flops by the micro-injection of the solution of both p-type and n-type materials in air. One of the potential platforms for low cost fabrication on flexible substrates is the use of inorganic semiconductor nanowires. Accordingly, the germanium nanowire FETs were fabricated and characterized. Conductivity enhanced PEDOT/PSS was employed as the electrode material for nanowire transistors to improve the electrical contacts to the source and drain. / text

The focus of this thesis involves development of highly transparent, n-channel, accumulation- mode thin-film transistors employing a zinc tin oxide (ZTO) channel layer. ZTO-based transparent thin-film transistors (TTFTs) show improved device performance compared to ZnO-based TTFTs. An estimated peak effective mobility for these devices as high as ~100 cm² V⁻¹sec⁻¹ has been observed, although effective mobilities in the range of 20-50 cm²V⁻¹sec⁻¹ are more common. This performance inconsistency may be due, in part, to the large device dimensions employed in developmental test structures and/or to shadow mask misalignment. Typical drain current on-to-off ratios are > 10⁶. Variation in the post-deposition annealing cycle is found to be an effective means to control the threshold voltage and to improve device performance. Optical characterization of these devices indicates ~84% transparency in the visible spectrum as viewed through the source/drain. Another aspect of this thesis research involves the utilization and extension of quantitative polycrystalline TFT device models with the intention of guiding the design and optimization of future TFTs. In particular, subthreshold conduction is assessed in order to estimate the bulk (and/or grain boundary) and interface trap densities. This leads to a consideration of threshold voltage and channel mobility extraction, as well as establishment of the turn-on voltage, V[subscript turn-on] Finally, a third aspect of this thesis research involves a new radio-frequency (RF) magnetron sputtering system, custom-designed and constructed at OSU by Chris Tasker. Contributions to the development of this tool include assisting in the design and implementation of the computer-controlled interlocks utilized for operation of the tool. The experimental flexibility of this new tool is discussed with respect to its applicability in the design and fabrication of future TTFTS. / Graduation date: 2004

Graduation date: 2006 / A discrete trap model is developed and employed for elucidation of thin-film transistor (TFT) device physics trends. An attractive feature of this model is that only two model parameters are required, the trap energy depth, E[subscript T], and the trap density, N[subscript T]. The most relevant trends occur when E[subscript T] is above the Fermi level. For this case drain current – drain voltage simulations indicate that the drain current decreases with an increase in N[subscript T] and E[subscript T]. The threshold voltage, V[subscript T], extracted from drain current – gate voltage (I[subscript D] – V[[subscript GS]) simulations, is found to be composed of two parts, V[subscript TRAP], the voltage required to fill all the traps and V[subscript ELECTRON], the voltage associated with electrons populating the conduction band. V[subscript T] moves toward a more positive voltage as N[subscript T] and E[subscript T] increase. The inverse subthreshold voltage swing, S, extracted from a log(I[subscript D]) – V[subscript GS] curve, increases as N[subscript T] and E[subscript T] increase. Finally, incremental mobility and average mobility versus gate voltage simulations indicate that the channel mobility decreases with increasing N[subscript T] and E[subscript T].

Present day data processing technology requires very high speed signal processing and data conversion rates. Traditionally, these circuits have been implemented in silicon MOS technology, whose high speed performance is limited, due to inherent material properties. Though relatively immature compared to silicon technology, GaAs integrated circuit technology appears to be a potential vehicle for realizing high-speed circuits because of its high electron mobility and low parasitic capacitance. One major drawback of GaAs technology has been the lack of complementary technology in contrast to silicon where CMOS technology has greatly facilitated the development of analog ICs. This thesis investigates the suitability of complementary GaAs Heterojunction FET integrated circuit technology for the realization of high sample-rate switched-capacitor circuits. In order to yield an accurate device model for the design work, model parameters of both n and p GaAs Heterojunction FET devices are extracted from measurement results. Based on the extraction results, a set of analog building blocks are presented. These circuits include a high bandwidth operational amplifier and a fast settling switch which are essential for high sample-rate circuits. A second order switched-capacitor low pass filter sampling at a clock rate of 100MHz is designed using the above building blocks. The designs studied predict better high frequency performance for C-HFETs compared to Si CMOS technology. / Graduation date: 1994

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