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Two MOS-Bipolar composite power semiconductor switching devices are proposed and experimentally demonstrated. These devices feature high voltage and high current capabilities, fast switching speeds, simple gate drive requirements, savings in chip area, reverse bias second breakdown ruggedness and large safe operating areas. Application characteristics of the devices for high frequency power inverter circuits are discussed. Monolithic integration of the two composite devices are also proposed. / Ph. D.

The objective of this thesis is to provide an initial demonstration of the feasibility of constructing highly transparent active electronic devices. Such a demonstration is successfully achieved in the fabrication of ZnO-based thin film transistors (TFTs) exhibiting transparency greater than ~90% in the visible portion of the electromagnetic spectrum and prototypical n-channel, enhancement mode TFT characteristics. Electrical characterization studies of these ZnO-based transparent TFTs and of CuYO��� / ZnO / ITO p-i-n heterojunction diodes serve to elucidate the mechanisms responsible for the behavior of these devices in particular, and of transparent electronic devices in general. Energy band analysis of the degenerate semiconductor / insulator heterojunction yields insight into the phenomenon of charge injection into an insulator, with important implications for the analysis of devices containing heterojunctions of this nature. Finally, a novel technique for simultaneously characterizing carrier injection into an insulator and interface channel formation, the capacitance-(voltage, frequency) [C-(V,f)] technique, is proposed and employed in the characterization of ZnO-based TFT structures. / Graduation date: 2003

Fabrication techniques and process integration considerations for amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) constitute the central theme of this dissertation. Within this theme three primary areas of focus are pursued. The first focus involves formulating a general framework for assessing passivation. Avoiding formation of an undesirable backside accumulation layer in an AOS bottom-gate TFT is accomplished by (i) choosing a passivation layer in which the charge neutrality level is aligned with (ideal case) or higher in energy than that of the semiconductor channel layer charge neutrality level, and (ii) depositing the passivation layer in such a manner that a negligible density of oxygen vacancies are present at the channel-passivation layer interface. Two AOS TFT passivation schemes are explored. Sputter-deposited zinc tin silicon oxide (ZTSO) appears promising for suppressing the effects of negative bias illumination stress (NBIS) with respect to ZTO and IGZO TFTs. Solution-deposited silicon dioxide is used as a barrier layer to subsequent PECVD silicon dioxide deposition, yielding ZTO TFT transfer curves showing that the dual-layer passivation process does not significantly alter ZTO TFT electrical characteristics. The second focus involves creating an adaptable back-end process compatible with flexible substrates. A detailed list of possible via formation techniques is presented with particular focus on non-traditional and adaptable techniques. Two of the discussed methods, "hydrophobic surface treatment" and "printed local insulator," are demonstrated and proven effective. The third focus is printing AOS TFT channel layers in order to create an adaptable and additive front-end integrated circuit fabrication scheme. Printed zinc indium aluminum oxide (ZIAO) and indium gallium zinc oxide (IGZO) channel layers are demonstrated using a SonoPlot piezoelectric printing system. Finally, challenges associated with printing electronic materials are discussed. Organic-based solutions are easier to print due to their ability to "stick" to the substrate and form well-defined patterns, but have poor electrical characteristics due to the weakness of organic bonds. Inorganic aqueous-based solutions demonstrate good electrical performance when deposited by spin coating, but are difficult to print because precise control of a substrate's hydrophillic/hydrophobic nature is required. However, precise control is difficult to achieve, since aqueous-based solutions either spread out or ball up on the substrate surface. Thickness control of any printed solution is always problematic due to surface wetting and the elliptical thickness profile of a dispensed solution. / Graduation date: 2013

This work investigates the effects of post-fabrication applied mechanical tensile strain on Silicon (Si) Bipolar Junction Transistor (BJT) and Silicon-Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices. Applied strain effects on MOSFET transistors are being heavily explored, both in academia and industry, as a possible alternative to dimensional scaling. This thesis focuses on how strain affects Si BJT and SiGe HBTs, where tensile strain is applied after the Integrated Circuit (IC) fabrication has been completed, using a unique mechanical method. The consequence of both biaxial and uniaxial strain application has been examined in this work. Chapter I gives a short introduction to the scope of this work, the motivation for conducting this research and the contributions of this experiment. Chapter II entails a brief discussion on Si bipolar and SiGe heterojunction bipolar device physics, which are key to the understanding of strain induced effects. Chapter III provides a thorough summary of the current state of research regarding applied strain, also known as Strain Engineering. It covers different types, orientations, and application techniques of strain. Chapter IV, highlights the details of this experiment, and also presents the measured results. It is observed that for this particular method of biaxial tensile strain application, the collector current (IC) and current gain degrades for both Si BJT and SiGe HBT. Base current (IB) decreases in Si BJT, though it increases for SiGe HBT after strain. Little or no change is noticed in the dynamic or ac small-signal characteristics like unity-gain cutoff frequency (fT) and base resistance (rBB) after strain. Uniaxially strained SiGe HBT samples showed similar results as the biaxial strain. This chapter also attempts to explain the origin of these strain induced changes. Chapter V, summarizes the finding of this experiment, and concludes the thesis with some future directions for this research.

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Two-dimensional numerical simulation was used to study the scaling properties of SOI p-MOSFETs. Based on the design criteria for the threshold voltage and DIBL, a set of design curves for different designs was developed. Data for subthreshold slope, SCE and threshold voltage sensitivity to silicon film thickness are also given. Results show that short-channel effects can be controlled by increasing the doping level or by thinning the silicon film thickness. The first approach is more effective for p+ gate design with high body doping, while the second approach is much more effective for n+ gate design with low body doping. Then+ gate design is more suited for the design of fully depleted (FD) devices since we need to keep the doping low to minimize the threshold adjustment implant dose and to use thin silicon films to control the SCE. The design of both p-MOSFET and Si 1-xGex p-MOSFET requires the implantation for the threshold voltage adjustment. The p+ gate design is more suited for the partially depleted (PD) or near-fully depleted device design since we need to use high doping for the threshold voltage adjustment and this results in large threshold voltage sensitivity to silicon film thickness for FD devices. The design of Si SOI p-MOSFET is done by properly adjusting the body doping. For the Si1-xGex SOI p-MOSFET large reduction in VTH requires large body doping. This increases the parasitic capacitances and slows down the device.

With increasing demand for complex and faster circuits, CMOS technologies are progressing towards the deep-submicron level. Process complexity increases dramatically, and costly techniques are to be developed to create dense field isolation and shallow junctions. Silicon-On-Insulator (SOI) may solve some of these problems. On the other hand, strained Si 1_xGex layers have been successfully grown on Si substrates and demonstrated much higher hole mobility than bulk Si. This can be used to build high-mobility p-MOSFET with a buried Si 1_xGex channel. A high mobility p-MOSFET would improve both the circuit speed and the level of integration. The purpose of the present study was to model and simulate the effective mobility (μeff) of SOI Si 1-xGex p-MOSFET, and to investigate the suitability of local mobility models provided by simulator MEDICI for studying SOI Si 1_xGex p-MOSFET. The simulation is performed by using the two-dimensional device simulation program (MEDICI). The design parameters, such as Si-cap thickness, Ge profile and back-gate bias, were also investigated. A long channel (6μ) and a short channel (0.25μ) SOI and bulk Si 1_xGex p MOSFET were used for the study. Simulation reveals good effective mobility μeff match with experimental results if Si Ge channel of p-MOSFET can simply be treated like a bulk silicon with mobility 250cm2 /Vs. Mobility models provided by MEDICI are two types: a) mobility model (SRFMOB2) that is dependent on transverse electric field only at Si/ Si02 interface, which means that the effective mobility is a function of grid spacing at Si/ Si02 interface, and b) mobility models (PRPMOB, LSMMOB and HPMOB) that are dependent on transverse electric field anywhere in the device. PRPMOB and LSMMOB produce very good μef f and are insensitive to the grid spacing. HP MOB gives slight over estimation of effective mobility μef f. Silicon cap thickness can significantly influence the effective mobility μef f. In general, the thin silicon cap have better effective mobility μef f, but it is limited by manufacturing process. Graded Si 1_:z:Ge:z: channel presents nearly 100% improvement of effective mobility μeff for p-MOSFET over its bulk counterpart. This improvement is sustained up to gate voltage of 2.5 V. Simulation also indicates that large improvement of effective mobility μef f requires higher Ge concentration at the top of SiGe channel with steep grading. The influence of back-gate bias on μeff is small, hence, SOI SiGe MOSFET is well suited to building CMOS circuits.

Since metal-oxide-semiconductor (MOS) devices have been adopted into integrated circuits, the endless demands for higher performance and lower power consumption have been a primary challenge and a technology-driver in the semiconductor electronics. The invention of complementary MOS (CMOS) technology in the 1980s, and the introduction of voltage and physical dimension scaling in the 1990s would be good examples to keep up with the everlasting demands. In the 2000s, technology continuously evolves and seeks for more power efficiency ways such as high-k dielectrics, metal gate electrodes, strained substrates, and high mobility channel materials. As a gate dielectric, silicon dioxide (SiO₂), most widely used in CMOS integrated circuits, has many prominent advantages, including a high quality interface (e.g. Dit ~ low 1010 cm-2eV-1), a good thermal stability in contact with silicon (Si), a large energy bandgap and the large energy band offsets in reference to Si, and a high quality dielectric itself. As the thickness of SiO₂ keeps shrinking, however, SiO₂ is facing its physical limitations from the viewpoint of gate dielectric leakage currents and reliability requirements. High-k dielectric materials have attracted extensive attention in the last decade due to their great potential for maintaining further down-scaling in equivalent oxide thickness (EOT) and a low dielectric leakage current. HfO₂ has been considered as one of the most promising candidates because of a high dielectric constant (k ~ 20-25), a large energy band gap (~ 6 eV) and the large band offsets (> 1.5 eV), and a good thermal stability. To enhance carrier mobility, strained substrates and high mobility channel materials have attracted a great deal of attention, thus III-V compound semiconductor substrates have emerged as one of possible candidates, in spite of several technical barriers, being believed as barriers so far. The absence of high quality and thermodynamically stable native oxide, like SiO₂ on Si, has been one such hurdle to implement MOS systems on III-V substrates. However, recently, there have been a number of remarkable improvements on MOS applications on them, inspiring more vigorous research activities. In this research, HfO2-based MOS capacitors and metal-oxidesemiconductor field effect transistors (MOSFETs) with a thin germanium (Ge) interfacial passivation layer (IPL) on III-V compound substrates were investigated. It was found that a thin Ge IPL could effectively passivate the surface of III-V substrate, consequently providing a high quality interface and an excellent gate oxide scalability. N-channel MOSFETs on GaAs, InGaAs, and InP substrates were successfully demonstrated and a minimum EOT of ~ 9 Å from MOS capacitors was achieved. This research has begun with GaAs substrate, and then expanded to InGaAs, InP, InAs, and InSb substrates, which eventually helped to understand the role of a Ge IPL and to guide future research direction. Overall, MOS devices on III-V substrates with an HfO₂ gate dielectric and a Ge IPL have demonstrated feasibility and potential for further investigations. / text